6e698b4dfe| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 9.810s | 250.101us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 10.950s | 499.087us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.615m | 17.438ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.141m | 3.263ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 14.960s | 798.350us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 10.950s | 499.087us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.141m | 3.263ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.193m | 22.626ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.350m | 1.238ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 55.400m | 57.442ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.096m | 2.819ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.157m | 8.973ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.270m | 4.840ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.924m | 56.376ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 58.183m | 244.571ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 57.150m | 52.466ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.004h | 470.585ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.134m | 12.753ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.450s | 43.371us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 2.340s | 28.426us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.090s | 341.381us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.090s | 341.381us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 9.810s | 250.101us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.950s | 499.087us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.141m | 3.263ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 45.650s | 2.788ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 9.810s | 250.101us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.950s | 499.087us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.141m | 3.263ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 45.650s | 2.788ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 628 | 630 | 99.68 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 7.643m | 6.830ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 7.643m | 6.830ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 7.643m | 6.830ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 7.643m | 6.830ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 21.046m | 17.580ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.297m | 4.738ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.297m | 4.738ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 7.643m | 6.830ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.115m | 2.533ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.096m | 2.819ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 58.183m | 244.571ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.096m | 2.819ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 55.400m | 57.442ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 55.400m | 57.442ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 26.400s | 3.598ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.485h | 84.751ms | 32 | 50 | 64.00 |
| V3 | TOTAL | 32 | 50 | 64.00 | |||
| TOTAL | 830 | 850 | 97.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 13 | 86.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.99 | 98.67 | 100.00 | 100.00 | 100.00 | 99.38 | 99.60 |
UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
5.alert_handler_stress_all_with_rand_reset.38296289648067245921010040911831411259496757769419811592769094037830276152384
Line 43762, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47196353601 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 47196353601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.alert_handler_stress_all_with_rand_reset.41472529710294452135531134265865753823706264664022667842495503937189344158137
Line 100829, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 355333032569 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 355333032569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
11.alert_handler_stress_all_with_rand_reset.21465555995670694530573923577172163046359033738187913503475250847972447416078
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8a7d24a9-0ffa-47af-9d86-81d88d10402d
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
19.alert_handler_sig_int_fail.96094194890371754810041262954571388874951484303789277296457484666371811035192
Line 419, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 1088113948 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 1088113948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:
37.alert_handler_stress_all_with_rand_reset.115414510188213499159796427165860991478260039927914809004343217721504468209580
Line 501, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 966131630 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 7 [0x7]) reg name: alert_handler_reg_block.classd_state
UVM_INFO @ 966131630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:330) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) has 1 failures:
39.alert_handler_stress_all.81838892751622804983498467529698579030357342551420251731160873908496506395804
Line 79430, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 73599621290 ps: (alert_handler_scoreboard.sv:330) [uvm_test_top.env.scoreboard] Check failed cycle_cnt <= exp_cycle (229 [0xe5] vs 75 [0x4b])
UVM_INFO @ 73599621290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---