3fd3528c8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 9.780s | 133.910us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 12.130s | 133.024us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.551m | 8.906ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 5.940m | 18.552ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 13.790s | 257.740us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 12.130s | 133.024us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 5.940m | 18.552ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.892m | 24.575ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.346m | 5.091ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 59.324m | 114.742ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.109m | 3.901ms | 48 | 50 | 96.00 |
| V2 | clk_skew | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.377m | 4.368ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.216m | 1.102ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 9.700m | 80.997ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 59.347m | 264.828ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 56.946m | 52.627ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.493h | 171.217ms | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.220m | 7.085ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.670s | 48.532us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 2.090s | 23.230us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 27.460s | 1.875ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 27.460s | 1.875ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 9.780s | 133.910us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 12.130s | 133.024us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.940m | 18.552ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 51.630s | 1.046ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 9.780s | 133.910us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 12.130s | 133.024us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.940m | 18.552ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 51.630s | 1.046ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 7.207m | 6.105ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 7.207m | 6.105ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 7.207m | 6.105ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 7.207m | 6.105ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 21.924m | 78.069ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.247m | 5.981ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.247m | 5.981ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 7.207m | 6.105ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.031m | 4.400ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.109m | 3.901ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 59.347m | 264.828ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.109m | 3.901ms | 48 | 50 | 96.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 59.324m | 114.742ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 59.324m | 114.742ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 31.620s | 652.891us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.259h | 756.798ms | 28 | 50 | 56.00 |
| V3 | TOTAL | 28 | 50 | 56.00 | |||
| TOTAL | 824 | 850 | 96.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.99 | 98.71 | 100.00 | 100.00 | 100.00 | 99.38 | 99.52 |
UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
1.alert_handler_stress_all_with_rand_reset.64273940966697337957799639843708686196717524698950367459846216685184690485154
Line 20997, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15181397184 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15181397184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.alert_handler_stress_all_with_rand_reset.62994289844572087533237827572379510222752395537590052997012288227317640059839
Line 46299, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 83212013443 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 83212013443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test alert_handler_lpg has 1 failures.
22.alert_handler_lpg.110276061186104921265384345283963548587985125360016063689473247406205817865689
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_lpg/latest/run.log
Job ID: smart:73a6961b-e14a-4cda-aadb-35795291f3c7
Test alert_handler_lpg_stub_clk has 1 failures.
37.alert_handler_lpg_stub_clk.71290243668369198056751434110377867502992928606176543310106539868628748826710
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:56c57e5e-2b2e-4736-9dc0-e38444644a0e
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
26.alert_handler_sig_int_fail.64392021300002970676425532544904689947204634967929971879541019356816016231256
Line 584, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 169005093 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 169005093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.alert_handler_sig_int_fail.43840446220114986267077247144374792550355035659241976538893107117411887901765
Line 500, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 372255040 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 372255040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
13.alert_handler_stress_all_with_rand_reset.25864293673045316300414057901946274230391957909343001250231899957797776028692
Line 181794, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 46407930966 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 46407930966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
35.alert_handler_stress_all_with_rand_reset.15194393381498554378540005430940211465386782857509004948076850392912777106158
Line 17284, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96932321707 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 96932321707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---