ALERT_HANDLER Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.330s	521.541us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.780s	127.897us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.274m	5.959ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.550m	6.347ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.180s	202.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.780s	127.897us	20	20	100.00
		alert_handler_csr_aliasing	4.550m	6.347ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.005m	19.996ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.224m	5.770ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.510m	398.593ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.033m	3.795ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.169m	4.403ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.348m	3.957ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.979m	32.505ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.338m	54.368ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.488m	51.716ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.143h	444.246ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	49.680s	2.142ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.610s	55.069us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.100s	28.476us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.860s	1.699ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.860s	1.699ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.330s	521.541us	5	5	100.00
		alert_handler_csr_rw	9.780s	127.897us	20	20	100.00
		alert_handler_csr_aliasing	4.550m	6.347ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.560s	701.359us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.330s	521.541us	5	5	100.00
		alert_handler_csr_rw	9.780s	127.897us	20	20	100.00
		alert_handler_csr_aliasing	4.550m	6.347ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.560s	701.359us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.043m	20.571ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.043m	20.571ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.043m	20.571ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.043m	20.571ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	23.437m	17.332ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
		alert_handler_tl_intg_err	1.510m	2.175ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.510m	2.175ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.043m	20.571ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.187m	4.678ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.033m	3.795ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.338m	54.368ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.033m	3.795ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.510m	398.593ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.510m	398.593ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.473m	2.233ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.771h	115.444ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			824	850	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.72	100.00	100.00	100.00	99.38	99.68

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test alert_handler_stress_all_with_rand_reset has 20 failures.
  - 2.alert_handler_stress_all_with_rand_reset.21379205112976288486397261580477186361108604959729626881485706954420595334320
    Line 12773, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10279845965 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10279845965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.47314615815214496484604204181959897357174773587551796151108416325459877108096
    Line 8923, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12776430986 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12776430986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test alert_handler_stress_all_with_rand_reset has 3 failures.
  - 30.alert_handler_stress_all_with_rand_reset.19920178287993265789704979542008806899658972363266968340431172524442618866231
    Line 151534, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53665695048 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 53665695048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.alert_handler_stress_all_with_rand_reset.86413252096323284610911188016347936678469895524419368688976249983350548793050
    Line 37919, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18872458756 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 18872458756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 0.alert_handler_stress_all_with_rand_reset.47128367612586981555874116543349515479599984780754116676966707104105781407837
    Line 73328, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56638272267 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 56638272267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 16.alert_handler_stress_all_with_rand_reset.111941223167489473141973255704733366422714927538685391749557803652067649184043
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:eed41a4e-9dcb-44b1-87b9-c08e2f67a989
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 39.alert_handler_stress_all_with_rand_reset.46500269663558712529506898819735829273943521553822576331995917490660606821646
    Line 11249, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12760498069 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 12760498069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be1c4a4f52`