ALERT_HANDLER Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.750s	124.025us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.500s	114.407us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.474m	33.531ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.264m	3.482ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.490s	204.428us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.500s	114.407us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	3.482ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.919m	7.051ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.306m	5.260ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.060m	165.441ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.347m	1.226ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.173m	2.439ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.299m	1.702ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.818m	88.492ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.106m	58.147ms	50	50	100.00
		alert_handler_lpg_stub_clk	48.873m	55.692ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	58.354m	238.825ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.480s	12.906ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.190s	172.384us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.810s	13.003us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.220s	1.321ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.220s	1.321ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.750s	124.025us	5	5	100.00
		alert_handler_csr_rw	8.500s	114.407us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	3.482ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.750s	526.781us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.750s	124.025us	5	5	100.00
		alert_handler_csr_rw	8.500s	114.407us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	3.482ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.750s	526.781us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.873m	5.770ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.873m	5.770ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.873m	5.770ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.873m	5.770ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.513m	25.752ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
		alert_handler_tl_intg_err	1.396m	2.448ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.396m	2.448ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.873m	5.770ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.079m	1.817ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.347m	1.226ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.106m	58.147ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.347m	1.226ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.060m	165.441ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.060m	165.441ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.350s	1.807ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.573h	595.080ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.66	100.00	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test alert_handler_stress_all_with_rand_reset has 20 failures.
  - 0.alert_handler_stress_all_with_rand_reset.1480346343196953241690091963381632615672131973234272984467937948642662284012
    Line 41852, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31057856452 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31057856452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.112630741821381454106078484056400290518547445994640614537495852734955450452918
    Line 25217, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24151970794 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24151970794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
- Test alert_handler_stress_all has 1 failures.
  - 8.alert_handler_stress_all.51929137695991331384670753488134425018414856953673722344702648376919303647563
    Line 45867, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 35790471315 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 35790471315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 41.alert_handler_stress_all_with_rand_reset.72247601966598329313685023579419390205390195082404055867142421371475456107387
    Line 32597, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8487313247 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 8487313247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 48.alert_handler_stress_all.6203945766698197300503520999345038406830577912298468465454568680917702471852
    Line 50867, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 9725593429 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 9725593429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8db2a18db1`