ALERT_HANDLER Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.740s	123.165us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.030s	142.045us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.075m	22.779ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.232m	14.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.020s	148.508us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.030s	142.045us	20	20	100.00
		alert_handler_csr_aliasing	4.232m	14.009ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.247m	10.484ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.349m	4.724ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.424m	61.001ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.345m	3.894ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.411m	10.511ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.216m	8.452ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.295m	72.900ms	49	50	98.00
V2	lpg	alert_handler_lpg	47.462m	109.122ms	49	50	98.00
		alert_handler_lpg_stub_clk	59.462m	100.786ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.077h	63.815ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	48.550s	3.290ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.010s	204.435us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.830s	15.185us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.680s	346.323us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.680s	346.323us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.740s	123.165us	5	5	100.00
		alert_handler_csr_rw	11.030s	142.045us	20	20	100.00
		alert_handler_csr_aliasing	4.232m	14.009ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.590s	4.933ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.740s	123.165us	5	5	100.00
		alert_handler_csr_rw	11.030s	142.045us	20	20	100.00
		alert_handler_csr_aliasing	4.232m	14.009ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.590s	4.933ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.249m	10.378ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.249m	10.378ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.249m	10.378ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.249m	10.378ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.838m	15.928ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
		alert_handler_tl_intg_err	1.467m	1.337ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.467m	1.337ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.249m	10.378ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.190m	4.391ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.345m	3.894ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	47.462m	109.122ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.345m	3.894ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.424m	61.001ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.424m	61.001ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	33.210s	648.184us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.363h	112.870ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			825	850	97.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.71	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test alert_handler_stress_all_with_rand_reset has 20 failures.

    • 0.alert_handler_stress_all_with_rand_reset.12104636908547102952997845933830453598127827978869425223266468912687092118804
      Line 5772, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16725989551 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16725989551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.44109974709683177455223611866447588987517737859603471893969118542767041458740
      Line 36236, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25711953477 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25711953477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 8.alert_handler_stress_all_with_rand_reset.82666204534327195332980913471337736543658639816511692260687301240728715703050
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:41664d81-3779-4bba-8b79-88e5abb6928d
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 19.alert_handler_stress_all_with_rand_reset.106803687252070375999988423384439891788618224604615582573169006201297846801729
      Line 29601, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16418358449 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (66 [0x42] vs 87 [0x57])
        UVM_INFO @ 16418358449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 21.alert_handler_ping_timeout.70036516773759879419322467215914235181837585218754314639356438402605220518993
      Line 420, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 574662768 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 2 [0x2]) reg name: alert_handler_reg_block.classb_accum_cnt
        UVM_INFO @ 574662768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 21.alert_handler_stress_all_with_rand_reset.50851197646402660250006954651762477819173384229247892288122293669897758130655
      Line 57417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53078343488 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 53078343488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalAlertIntFail has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 31.alert_handler_lpg.110041743562687805857971989128628288801013648084485824314017884145150307573348
      Line 1064, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_lpg/latest/run.log

        UVM_ERROR @ 1374537688 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 0, local_alert_type LocalAlertIntFail
        UVM_INFO @ 1374537688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.06.28_12.13.16
• 2024.06.27_11.29.56
• 2024.06.26_11.27.33
• 2024.06.25_11.50.19
• 2024.06.24_08.49.02
• 2024.06.23_08.12.18