ALERT_HANDLER Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	12.020s	140.430us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.110s	783.711us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.692m	34.127ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.645m	4.659ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.380s	387.685us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.110s	783.711us	20	20	100.00
		alert_handler_csr_aliasing	2.645m	4.659ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.284m	5.461ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.084m	2.190ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.479m	226.820ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	33.382m	200.000ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.306m	2.618ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.214m	3.692ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.043m	58.512ms	49	50	98.00
V2	lpg	alert_handler_lpg	57.057m	256.841ms	49	50	98.00
		alert_handler_lpg_stub_clk	58.922m	57.472ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.085h	64.949ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.134m	1.597ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.530s	99.423us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.760s	9.972us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.580s	1.655ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.580s	1.655ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	12.020s	140.430us	5	5	100.00
		alert_handler_csr_rw	10.110s	783.711us	20	20	100.00
		alert_handler_csr_aliasing	2.645m	4.659ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.040s	651.322us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	12.020s	140.430us	5	5	100.00
		alert_handler_csr_rw	10.110s	783.711us	20	20	100.00
		alert_handler_csr_aliasing	2.645m	4.659ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.040s	651.322us	20	20	100.00
V2		TOTAL			624	630	99.05
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.800m	6.777ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.800m	6.777ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.800m	6.777ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.800m	6.777ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.621m	18.863ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
		alert_handler_tl_intg_err	1.566m	1.277ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.566m	1.277ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.800m	6.777ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.245m	7.626ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	33.382m	200.000ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.057m	256.841ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	33.382m	200.000ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.479m	226.820ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.479m	226.820ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	34.760s	858.049us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.539h	152.761ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			822	850	96.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	10	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.67	100.00	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test alert_handler_stress_all_with_rand_reset has 20 failures.
  - 0.alert_handler_stress_all_with_rand_reset.70003478780523321565554695807100114970266439976010238682229055588840311731445
    Line 85904, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 586684221917 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 586684221917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.alert_handler_stress_all_with_rand_reset.60262667108731529579795043000175237178065570730275584935598118932355345020813
    Line 12572, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24194659589 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24194659589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 22.alert_handler_stress_all_with_rand_reset.20883008211709578533177618404280810898364010694409761343592946029583163542595
    Line 1166, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3217946715 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3217946715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.alert_handler_stress_all_with_rand_reset.23964606859685325116277260715634137855277928485854134682367099235103691488393
    Line 12011, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8747866204 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8747866204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_entropy has 1 failures.
  - 29.alert_handler_entropy.75386869656835332655414044070046822744703269444587417417843941303256781685443
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_entropy/latest/run.log
```
  Job ID: smart:a0cca8b3-68b3-410f-bfc2-9dc451951188
```
- Test alert_handler_lpg has 1 failures.
  - 38.alert_handler_lpg.41302274545918578976994193722605850872103337293060067329350146166471641818217
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_lpg/latest/run.log
```
  Job ID: smart:bbaba183-b5e1-4f78-b4a2-42b2f8f30820
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscPingFail has 1 failures:
- Test alert_handler_ping_timeout has 1 failures.
  - 1.alert_handler_ping_timeout.107573885394287385650637083219198442984793147345864730604667718747431444697330
    Line 339, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest/run.log
```
  UVM_ERROR @ 324952827 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscPingFail
  UVM_INFO @ 324952827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 2.alert_handler_stress_all.6208649982876308970305991501546906891401827507697371556182084328756460809301
    Line 49775, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 470600161611 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 5 [0x5]) reg name: alert_handler_reg_block.classc_state
  UVM_INFO @ 470600161611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 12.alert_handler_stress_all.9304870083326413518088780912081703472925377591734994442420356958950554680981
    Line 6008, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 12100332204 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 12100332204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 41.alert_handler_sig_int_fail.31014339093061769122941706153170559356378351587814888607771516831922709335710
    Line 335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b33f0bcb4a`