ALERT_HANDLER Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.590s	130.426us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.720s	332.026us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.258m	17.824ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.517m	17.818ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.450s	255.560us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.720s	332.026us	20	20	100.00
		alert_handler_csr_aliasing	5.517m	17.818ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.194m	5.322ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.231m	4.759ms	50	50	100.00
V2	entropy	alert_handler_entropy	50.051m	972.921ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.218m	999.462us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.215m	21.482ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.203m	2.372ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.245m	190.534ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.035m	53.544ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.101m	603.763ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.185h	291.209ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.295m	10.830ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.640s	197.846us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.900s	16.826us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.990s	421.390us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.990s	421.390us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.590s	130.426us	5	5	100.00
		alert_handler_csr_rw	8.720s	332.026us	20	20	100.00
		alert_handler_csr_aliasing	5.517m	17.818ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.350s	1.448ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.590s	130.426us	5	5	100.00
		alert_handler_csr_rw	8.720s	332.026us	20	20	100.00
		alert_handler_csr_aliasing	5.517m	17.818ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.350s	1.448ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.628m	81.153ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.628m	81.153ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.628m	81.153ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.628m	81.153ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.572m	17.762ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
		alert_handler_tl_intg_err	1.295m	915.220us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.295m	915.220us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.628m	81.153ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.339m	5.736ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.218m	999.462us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.035m	53.544ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.218m	999.462us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	50.051m	972.921ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	50.051m	972.921ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	29.510s	1.932ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.838h	575.081ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.69	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

  • Test alert_handler_stress_all_with_rand_reset has 13 failures.

    • 1.alert_handler_stress_all_with_rand_reset.115049376640748752375217549699717854960554789676805896657827919307004443782679
      Line 22662, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31415443193 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31415443193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.87181549001554084469007906376256544658423949754508890200230947753476015995145
      Line 83780, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 103794389085 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 103794389085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 38.alert_handler_stress_all_with_rand_reset.115756432287504813216400976951726395857157312914859235683808040659822583997054
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e4ded7f8-9e68-4372-9dac-5b80a6154802
      

  • Test alert_handler_lpg has 1 failures.

    • 45.alert_handler_lpg.51373395736518570004356887282179096404972848648084852219302170152775945017545
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_lpg/latest/run.log

        Job ID: smart:b6e30ba1-c3ad-4071-ae3f-e0d879de0b89
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 36.alert_handler_stress_all_with_rand_reset.98368147914691662488249198309778205683486277890390321632856739997878289245401
      Line 41314, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8813478031 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 8813478031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.06.30_11.34.08
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• 2024.06.28_12.13.16
• 2024.06.27_11.29.56
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