ALERT_HANDLER Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.720s	1.354ms	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.760s	131.074us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.093m	85.557ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.648m	4.582ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.650s	1.443ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.760s	131.074us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	4.582ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.296m	15.528ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.272m	5.182ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.177m	52.973ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.290m	1.153ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.257m	4.926ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.204m	9.121ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.669m	15.335ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.646m	225.705ms	49	50	98.00
		alert_handler_lpg_stub_clk	51.080m	56.277ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.307h	76.235ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.158m	3.383ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.370s	197.284us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.150s	27.390us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	30.470s	602.577us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	30.470s	602.577us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.720s	1.354ms	5	5	100.00
		alert_handler_csr_rw	9.760s	131.074us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	4.582ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.480s	1.100ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.720s	1.354ms	5	5	100.00
		alert_handler_csr_rw	9.760s	131.074us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	4.582ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.480s	1.100ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.059m	13.670ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.059m	13.670ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.059m	13.670ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.059m	13.670ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.488m	16.878ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
		alert_handler_tl_intg_err	1.482m	4.979ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.482m	4.979ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.059m	13.670ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.002m	6.322ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.290m	1.153ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.646m	225.705ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.290m	1.153ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.177m	52.973ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.177m	52.973ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.320s	437.635us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.791h	345.482ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.72	99.97	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test alert_handler_stress_all_with_rand_reset has 13 failures.
  - 1.alert_handler_stress_all_with_rand_reset.92708029044939584656819490131371795939998612656451690702156573613829453993671
    Line 7692, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15270499838 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15270499838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.alert_handler_stress_all_with_rand_reset.97901706712933871824040687863238288597121326379563911565419270623813069547162
    Line 11711, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16959167686 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16959167686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 12.alert_handler_lpg.68079529902363260381536688279739630160145857152376807472389185654487334593455
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_lpg/latest/run.log
```
  Job ID: smart:159ba27b-38ce-4cd9-a30f-1faf874006eb
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 31.alert_handler_stress_all_with_rand_reset.78534172835537609525729146035218322757752547046523991901194366738225715576650
    Line 46238, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33919465209 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 33919465209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 34.alert_handler_stress_all_with_rand_reset.14189960447475793249693501518195229474207285111436249609459558992540245110808
    Line 666, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 492310675 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 492310675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eb56ef55d0`