ALERT_HANDLER Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.460s	45.504us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.900s	493.643us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.415m	15.092ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.669m	1.214ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.370s	432.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.900s	493.643us	20	20	100.00
		alert_handler_csr_aliasing	2.669m	1.214ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.784m	12.116ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	57.250s	2.207ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.405m	52.759ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.173m	1.111ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.160m	1.166ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.222m	5.068ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.077m	54.235ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.478m	111.487ms	49	50	98.00
		alert_handler_lpg_stub_clk	59.358m	225.253ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.310h	86.422ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	38.280s	3.243ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.020s	45.944us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.270s	28.478us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.140s	701.754us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.140s	701.754us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.460s	45.504us	5	5	100.00
		alert_handler_csr_rw	9.900s	493.643us	20	20	100.00
		alert_handler_csr_aliasing	2.669m	1.214ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.350s	1.419ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.460s	45.504us	5	5	100.00
		alert_handler_csr_rw	9.900s	493.643us	20	20	100.00
		alert_handler_csr_aliasing	2.669m	1.214ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.350s	1.419ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.510m	10.690ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.510m	10.690ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.510m	10.690ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.510m	10.690ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.634m	16.554ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
		alert_handler_tl_intg_err	1.453m	2.496ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.453m	2.496ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.510m	10.690ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.096m	2.191ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.173m	1.111ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.478m	111.487ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.173m	1.111ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.405m	52.759ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.405m	52.759ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.130s	428.935us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.339h	283.467ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			833	850	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.66	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test alert_handler_stress_all_with_rand_reset has 14 failures.

    • 1.alert_handler_stress_all_with_rand_reset.3265051567357477921207637733835324038836098569755482851121442717000987077584
      Line 22572, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16537721080 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16537721080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.65151258296597773361006121678174771232166057427030162556073563475736914555946
      Line 11612, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78470490028 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 78470490028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_lpg has 1 failures.

    • 17.alert_handler_lpg.73985096861965463941214154185399173988847370690218580234611038359645723000002
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_lpg/latest/run.log

        Job ID: smart:3600a48e-d672-4c80-b78e-a17571aa0b31
      

  • Test alert_handler_entropy has 1 failures.

    • 40.alert_handler_entropy.93430953948250581891782964261187466999116197994798142263685435934507605754022
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_entropy/latest/run.log

        Job ID: smart:0ff66717-823a-416f-82f2-8963973917f3
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 47.alert_handler_stress_all_with_rand_reset.2151502386626183034324764540309344153008092259776385845481778033229184690994
      Line 65218, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19553106381 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 19553106381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.07.02_04.36.00
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