ALERT_HANDLER Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.260s	261.057us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.110s	289.725us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.592m	10.186ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.593m	4.044ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.370s	297.075us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.110s	289.725us	20	20	100.00
		alert_handler_csr_aliasing	4.593m	4.044ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.789m	5.638ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.226m	2.457ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.725m	246.726ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.076m	1.114ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.046m	805.372us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.307m	1.723ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.886m	130.816ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.645m	58.884ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.132m	50.875ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.273h	161.869ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.272m	3.389ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.790s	48.818us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.240s	23.520us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	32.490s	1.754ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	32.490s	1.754ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.260s	261.057us	5	5	100.00
		alert_handler_csr_rw	10.110s	289.725us	20	20	100.00
		alert_handler_csr_aliasing	4.593m	4.044ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.910s	9.665ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.260s	261.057us	5	5	100.00
		alert_handler_csr_rw	10.110s	289.725us	20	20	100.00
		alert_handler_csr_aliasing	4.593m	4.044ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.910s	9.665ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.126m	4.083ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.126m	4.083ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.126m	4.083ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.126m	4.083ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.515m	17.112ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
		alert_handler_tl_intg_err	1.486m	4.720ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.486m	4.720ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.126m	4.083ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.263m	5.212ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.076m	1.114ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.645m	58.884ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.076m	1.114ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.725m	246.726ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.725m	246.726ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	2.729m	4.355ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.543h	1.844s	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			825	850	97.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.70	100.00	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test alert_handler_stress_all_with_rand_reset has 21 failures.
  - 2.alert_handler_stress_all_with_rand_reset.34456346394583430389400001799730868537621918075943999635449991383083166163586
    Line 46727, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46917548609 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 46917548609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.49328618322834232356604311730309036912704930716077535144148292137223953663508
    Line 15404, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27385170904 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10027 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27385170904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 32.alert_handler_stress_all_with_rand_reset.39329063877235961984581797555959266729954130827069725860921134246767350977704
    Line 5610, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4564523436 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4564523436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.alert_handler_stress_all_with_rand_reset.41910250264183784464264676402601858073040931675805586190088486295326159950604
    Line 43198, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173108278184 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 173108278184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 6.alert_handler_stress_all_with_rand_reset.1429736801583764781917299486432576805052502766903501299518482387907962950766
    Line 110585, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64109327983 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 64109327983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 14.alert_handler_sig_int_fail.70772913343602474810936995413563235801275763983614096419245766165373145116472
    Line 665, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 565261852 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 565261852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`