ALERT_HANDLER Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.180s	195.062us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.360s	877.051us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.040m	50.231ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.671m	27.109ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.550s	261.790us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.360s	877.051us	20	20	100.00
		alert_handler_csr_aliasing	5.671m	27.109ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.645m	9.393ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.373m	5.957ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.529m	54.147ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.154m	2.274ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.228m	2.139ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.087m	6.642ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.787m	77.913ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.765m	234.146ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.250m	54.230ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.115h	274.105ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.269m	1.718ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.460s	190.520us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.420s	58.316us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.620s	1.448ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.620s	1.448ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.180s	195.062us	5	5	100.00
		alert_handler_csr_rw	10.360s	877.051us	20	20	100.00
		alert_handler_csr_aliasing	5.671m	27.109ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.500s	1.334ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.180s	195.062us	5	5	100.00
		alert_handler_csr_rw	10.360s	877.051us	20	20	100.00
		alert_handler_csr_aliasing	5.671m	27.109ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.500s	1.334ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.794m	11.777ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.794m	11.777ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.794m	11.777ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.794m	11.777ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.933m	30.629ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
		alert_handler_tl_intg_err	1.316m	1.274ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.316m	1.274ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.794m	11.777ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.410m	5.739ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.154m	2.274ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.765m	234.146ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.154m	2.274ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.529m	54.147ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.529m	54.147ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	30.490s	674.985us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.636h	596.907ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.66	100.00	100.00	100.00	99.38	99.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 3.alert_handler_stress_all_with_rand_reset.90695740967255430658298168107257300763134310055130839832135992225471231816725
      Line 22334, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22317367585 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22317367585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.81021218898570447781589597034091296775126877108295900743280020867738333835246
      Line 36106, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26052942697 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26052942697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 35.alert_handler_stress_all_with_rand_reset.27017023508955872228816692097364905201616397620156791045274889606748496614813
      Line 38911, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36804418441 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 36804418441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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