ALERT_HANDLER Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	12.540s	253.899us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.490s	470.784us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.405m	16.400ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.683m	13.141ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.990s	1.251ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.490s	470.784us	20	20	100.00
		alert_handler_csr_aliasing	4.683m	13.141ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.472m	6.153ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.332m	2.616ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.740m	216.374ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.252m	4.550ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	59.620s	854.478us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.270m	9.414ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.489m	29.902ms	50	50	100.00
V2	lpg	alert_handler_lpg	50.566m	56.113ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.004m	225.536ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.029h	277.959ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.690s	1.407ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.570s	46.184us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.160s	25.985us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.530s	1.087ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.530s	1.087ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	12.540s	253.899us	5	5	100.00
		alert_handler_csr_rw	9.490s	470.784us	20	20	100.00
		alert_handler_csr_aliasing	4.683m	13.141ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.480s	659.245us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	12.540s	253.899us	5	5	100.00
		alert_handler_csr_rw	9.490s	470.784us	20	20	100.00
		alert_handler_csr_aliasing	4.683m	13.141ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.480s	659.245us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.648m	23.512ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.648m	23.512ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.648m	23.512ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.648m	23.512ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.052m	15.047ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
		alert_handler_tl_intg_err	1.404m	9.033ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.404m	9.033ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.648m	23.512ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.136m	3.793ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.252m	4.550ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	50.566m	56.113ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.252m	4.550ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.740m	216.374ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.740m	216.374ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	44.420s	1.576ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.867h	365.568ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.75	100.00	100.00	100.00	99.38	99.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test alert_handler_stress_all_with_rand_reset has 19 failures.
  - 2.alert_handler_stress_all_with_rand_reset.90059884725784526509865112258650338899702067194173812645300516687381883114103
    Line 61838, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46913091188 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 46913091188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.39302501499324356853493926333855763348863605942225511213190845104131376881237
    Line 98477, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 200528266960 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 200528266960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 18.alert_handler_stress_all_with_rand_reset.38671301112436750125629351075648547417660953842950791262033747668314781674921
    Line 26688, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28025965753 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28025965753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 24.alert_handler_stress_all_with_rand_reset.98066754583295313199448266153049050897126729466678605184292054396303582314239
    Line 4393, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6024731061 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 6024731061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalAlertIntFail has 1 failures:
- Test alert_handler_entropy has 1 failures.
  - 37.alert_handler_entropy.28402658879261419562102466518169917248870764505652889104598731545446599975001
    Line 27389, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_entropy/latest/run.log
```
  UVM_ERROR @ 24821820743 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 0, local_alert_type LocalAlertIntFail
  UVM_INFO @ 24821820743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 47.alert_handler_stress_all_with_rand_reset.44805648468616237433643753278722865110738820536196582996748819798064802369796
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7ce06ec0-6e06-4b77-86f7-83930876a169
```

ALERT_HANDLER Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`