ALERT_HANDLER Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.170s	44.839us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.210s	498.607us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.542m	8.925ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.581m	4.146ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.500s	1.539ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.210s	498.607us	20	20	100.00
		alert_handler_csr_aliasing	4.581m	4.146ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.552m	17.560ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.151m	4.075ms	50	50	100.00
V2	entropy	alert_handler_entropy	50.658m	99.656ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	56.360s	6.264ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	58.240s	4.118ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.217m	4.624ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.395m	26.501ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.038m	60.682ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.438m	74.906ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	56.438m	275.714ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	46.250s	1.085ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.700s	58.234us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.650s	12.814us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.600s	336.709us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.600s	336.709us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.170s	44.839us	5	5	100.00
		alert_handler_csr_rw	8.210s	498.607us	20	20	100.00
		alert_handler_csr_aliasing	4.581m	4.146ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.090s	2.805ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.170s	44.839us	5	5	100.00
		alert_handler_csr_rw	8.210s	498.607us	20	20	100.00
		alert_handler_csr_aliasing	4.581m	4.146ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.090s	2.805ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.037m	17.735ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.037m	17.735ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.037m	17.735ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.037m	17.735ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	16.310m	12.923ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
		alert_handler_tl_intg_err	1.076m	1.851ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.076m	1.851ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.037m	17.735ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.212m	4.574ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	56.360s	6.264ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.038m	60.682ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	56.360s	6.264ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	50.658m	99.656ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	50.658m	99.656ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	54.160s	1.437ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.265h	586.535ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			833	850	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.72	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
  • Test alert_handler_stress_all_with_rand_reset has 16 failures.

    • 0.alert_handler_stress_all_with_rand_reset.94417668111291745512216676295589337886083446850782701206211212744084193204294
      Line 23923, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41551685323 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 41551685323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.33797208443939334101399105164895446087542540608035172351391525332331217990011
      Line 16334, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15354137235 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15354137235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 34.alert_handler_stress_all_with_rand_reset.16242998185443688139144937797641787510567162457684297616726734922347001310801
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:71ee1076-b0ac-4c9f-8c98-1efa4ec96e07
      

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