ALERT_HANDLER Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.840s	1.266ms	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.970s	128.658us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.155m	34.139ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.004m	8.481ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.150s	353.960us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.970s	128.658us	20	20	100.00
		alert_handler_csr_aliasing	5.004m	8.481ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.591m	5.909ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.353m	8.827ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.728m	62.217ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.281m	21.806ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.235m	5.025ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.175m	1.156ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.036m	62.798ms	49	50	98.00
V2	lpg	alert_handler_lpg	53.181m	118.629ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.498m	238.722ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	56.180m	62.773ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	30.010s	628.498us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.860s	67.850us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.630s	39.024us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.130s	368.263us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.130s	368.263us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.840s	1.266ms	5	5	100.00
		alert_handler_csr_rw	9.970s	128.658us	20	20	100.00
		alert_handler_csr_aliasing	5.004m	8.481ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.380s	1.338ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.840s	1.266ms	5	5	100.00
		alert_handler_csr_rw	9.970s	128.658us	20	20	100.00
		alert_handler_csr_aliasing	5.004m	8.481ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.380s	1.338ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.279m	21.756ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.279m	21.756ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.279m	21.756ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.279m	21.756ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.501m	17.825ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
		alert_handler_tl_intg_err	1.564m	4.770ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.564m	4.770ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.279m	21.756ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.216m	1.212ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.281m	21.806ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.181m	118.629ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.281m	21.806ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.728m	62.217ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.728m	62.217ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.860s	1.856ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.495h	185.052ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			839	850	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.72	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:

  • Test alert_handler_stress_all_with_rand_reset has 8 failures.

    • 3.alert_handler_stress_all_with_rand_reset.42769938689705276554521742523072460989141296013446888154691241965712555942734
      Line 16484, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33642043513 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 33642043513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.alert_handler_stress_all_with_rand_reset.41687458487439385891913940496003787718997921058069162946942009057938287717611
      Line 7973, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6759482515 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6759482515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 5.alert_handler_stress_all.25095971543588182248704905159623527288029099476102329375868088727773630562600
      Line 5260, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 10278838335 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (682 [0x2aa] vs 909 [0x38d])
        UVM_INFO @ 10278838335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 19.alert_handler_stress_all_with_rand_reset.31654395840159020807147029909170063213719421903636763328150364042260252336696
      Line 13332, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11068787430 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 11068787430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscPingFail has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 47.alert_handler_ping_timeout.52803309383960725855464375763722218352393501302253309862176349608939076255527
      Line 593, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 1889459280 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscPingFail
        UVM_INFO @ 1889459280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.07.06_11.04.02
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