ALERT_HANDLER Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.370s	380.258us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.810s	130.935us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.764m	11.410ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.886m	5.736ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.230s	184.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.810s	130.935us	20	20	100.00
		alert_handler_csr_aliasing	2.886m	5.736ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.103m	31.669ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.168m	4.154ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.642m	242.782ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.076m	3.883ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.199m	2.749ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.307m	4.569ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.937m	16.087ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.135m	57.335ms	49	50	98.00
		alert_handler_lpg_stub_clk	48.461m	104.880ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.145h	178.487ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	59.200s	1.347ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.350s	51.161us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.270s	31.182us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.260s	679.209us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.260s	679.209us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.370s	380.258us	5	5	100.00
		alert_handler_csr_rw	9.810s	130.935us	20	20	100.00
		alert_handler_csr_aliasing	2.886m	5.736ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.270s	2.831ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.370s	380.258us	5	5	100.00
		alert_handler_csr_rw	9.810s	130.935us	20	20	100.00
		alert_handler_csr_aliasing	2.886m	5.736ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.270s	2.831ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.494m	5.956ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.494m	5.956ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.494m	5.956ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.494m	5.956ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.241m	61.892ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
		alert_handler_tl_intg_err	1.238m	2.771ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.238m	2.771ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.494m	5.956ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.114m	6.663ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.076m	3.883ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.135m	57.335ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.076m	3.883ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.642m	242.782ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.642m	242.782ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	30.210s	583.981us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.479h	469.411ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.70	100.00	100.00	100.00	99.38	99.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 0.alert_handler_stress_all_with_rand_reset.26841989791231806251571040626524274185006978372859768143243661749608391112111
    Line 27114, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 580742802039 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 580742802039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.28350111217304510451911569179109454947592260055856029130426265907151072621557
    Line 21137, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81138859852 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 81138859852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:475) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 13.alert_handler_lpg.16442457715665048111690017308140140111811403958292691770277051679101211927087
    Line 740, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_lpg/latest/run.log
```
  UVM_ERROR @ 809942524 ps: (alert_handler_scoreboard.sv:475) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (10 [0xa] vs 11 [0xb]) reg name: intr_state
  UVM_INFO @ 809942524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 43.alert_handler_stress_all.3067210710521440880112015364393095479450604000438923087607053631837059262162
    Line 2719, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 1716689168 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1716689168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 43.alert_handler_stress_all_with_rand_reset.57417055698614862131562940033551257463218444094542896145095456775737031019573
    Line 126552, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 94543716939 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
  UVM_INFO @ 94543716939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`