ALERT_HANDLER Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.920s	75.177us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.820s	187.924us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.549m	21.924ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.429m	3.282ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.420s	210.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.820s	187.924us	20	20	100.00
		alert_handler_csr_aliasing	4.429m	3.282ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.872m	11.270ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.274m	5.153ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.662m	202.921ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.078m	1.070ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.268m	5.277ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.166m	2.351ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.417m	15.501ms	49	50	98.00
V2	lpg	alert_handler_lpg	48.907m	211.761ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.527m	59.573ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.008h	126.252ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.284m	1.829ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.640s	61.212us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.130s	22.025us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.790s	4.480ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.790s	4.480ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.920s	75.177us	5	5	100.00
		alert_handler_csr_rw	10.820s	187.924us	20	20	100.00
		alert_handler_csr_aliasing	4.429m	3.282ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.340s	2.651ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.920s	75.177us	5	5	100.00
		alert_handler_csr_rw	10.820s	187.924us	20	20	100.00
		alert_handler_csr_aliasing	4.429m	3.282ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.340s	2.651ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.474m	22.248ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.474m	22.248ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.474m	22.248ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.474m	22.248ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.142m	92.267ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
		alert_handler_tl_intg_err	47.800s	331.248us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	47.800s	331.248us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.474m	22.248ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.116m	1.166ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.078m	1.070ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	48.907m	211.761ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.078m	1.070ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.662m	202.921ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.662m	202.921ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	54.210s	1.286ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.305h	1.232s	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.99	98.62	99.97	100.00	100.00	99.38	99.40

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 1.alert_handler_stress_all_with_rand_reset.75655094851162967057041595892351940054053245223646093380414979033198102819352
    Line 10814, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31100265417 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31100265417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.18398042107546246230157107472128941150368444236041561572156750367357368192137
    Line 2634, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2142335474 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2142335474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 20.alert_handler_stress_all_with_rand_reset.102481978151285415245757118892380519662283367270450441463365785974290243630233
    Line 73810, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 247526912242 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 247526912242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.alert_handler_stress_all_with_rand_reset.73778065353078149591436540726048339275217620482328385673812121198672704065422
    Line 5147, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15383743403 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15383743403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 16.alert_handler_lpg_stub_clk.111787626324992673984509219790240406077746814347711411532434863517001461747842
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:194e97a6-6104-4a79-bd0d-72c48f88b7b7
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscPingFail has 1 failures:
- Test alert_handler_ping_timeout has 1 failures.
  - 27.alert_handler_ping_timeout.381363817122073469462992253235217239846865877885941392976849350539347210273
    Line 339, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log
```
  UVM_ERROR @ 738468570 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscPingFail
  UVM_INFO @ 738468570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 44.alert_handler_stress_all.27014426493088482030380859945028564129953673494575075853103432298872414901289
    Line 78816, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 126251528035 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 126251528035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 46.alert_handler_stress_all_with_rand_reset.22305239854251312779840292128356179555645949564830285181217102614274777452690
    Line 100944, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131249840272 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 131249840272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`