ALERT_HANDLER Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.450s	367.942us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.910s	209.966us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.222m	34.204ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.892m	4.589ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.060s	665.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.910s	209.966us	20	20	100.00
		alert_handler_csr_aliasing	2.892m	4.589ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.299m	6.201ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.240m	1.661ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.734m	50.498ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.091m	775.355us	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.249m	6.899ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.256m	3.130ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.641m	17.093ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.564m	127.376ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.863m	121.666ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.168h	73.542ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.680s	5.853ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.260s	162.513us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.370s	30.034us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.870s	1.397ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.870s	1.397ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.450s	367.942us	5	5	100.00
		alert_handler_csr_rw	9.910s	209.966us	20	20	100.00
		alert_handler_csr_aliasing	2.892m	4.589ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.290s	745.798us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.450s	367.942us	5	5	100.00
		alert_handler_csr_rw	9.910s	209.966us	20	20	100.00
		alert_handler_csr_aliasing	2.892m	4.589ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.290s	745.798us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.527m	4.911ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.527m	4.911ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.527m	4.911ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.527m	4.911ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.584m	16.950ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
		alert_handler_tl_intg_err	1.507m	4.429ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.507m	4.429ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.527m	4.911ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.322m	5.560ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.091m	775.355us	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.564m	127.376ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.091m	775.355us	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.734m	50.498ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.734m	50.498ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.240s	539.788us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.466h	92.196ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			833	850	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.78	100.00	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test alert_handler_stress_all_with_rand_reset has 14 failures.
  - 3.alert_handler_stress_all_with_rand_reset.61870341145038762304624589574898395298432739380219071303851477014569849147909
    Line 5525, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107394330121 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107394330121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.alert_handler_stress_all_with_rand_reset.24053835834939272240797024218425763493486876674163084591845628895660943169285
    Line 12139, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10375036641 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10375036641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 9.alert_handler_stress_all.100693830248534852839814994829830091257374097845300573153849476699759090140120
    Line 57850, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 100085043106 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156 [0x9c] vs 155 [0x9b]) reg name: alert_handler_reg_block.classa_accum_cnt
  UVM_INFO @ 100085043106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 24.alert_handler_sig_int_fail.36505559657416112225928421387801803847657065438834837770107974119606978593929
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 579964908 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 579964908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 43.alert_handler_sig_int_fail.27865332761656668178538317937008375866255745864207842621202887272930014177442
    Line 1076, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 653762699 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 653762699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39211701b5`