ALERT_HANDLER Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.140s	199.855us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.190s	594.323us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.049m	23.737ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.535m	41.892ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.350s	189.131us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.190s	594.323us	20	20	100.00
		alert_handler_csr_aliasing	4.535m	41.892ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.014m	42.834ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.258m	2.658ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.840m	459.865ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.212m	1.107ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.163m	2.114ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.467m	4.375ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.572m	56.570ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.694m	62.663ms	49	50	98.00
		alert_handler_lpg_stub_clk	57.472m	231.742ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.039h	116.732ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.800s	4.876ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.360s	50.161us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.850s	18.548us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	19.660s	1.142ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	19.660s	1.142ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.140s	199.855us	5	5	100.00
		alert_handler_csr_rw	10.190s	594.323us	20	20	100.00
		alert_handler_csr_aliasing	4.535m	41.892ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.160s	2.257ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.140s	199.855us	5	5	100.00
		alert_handler_csr_rw	10.190s	594.323us	20	20	100.00
		alert_handler_csr_aliasing	4.535m	41.892ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.160s	2.257ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.992m	12.677ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.992m	12.677ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.992m	12.677ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.992m	12.677ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.608m	126.613ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
		alert_handler_tl_intg_err	1.397m	5.171ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.397m	5.171ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.992m	12.677ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.332m	21.495ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.212m	1.107ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.694m	62.663ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.212m	1.107ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.840m	459.865ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.840m	459.865ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	2.711m	4.354ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.672h	359.008ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			821	850	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.65	99.97	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test alert_handler_stress_all_with_rand_reset has 25 failures.

    • 0.alert_handler_stress_all_with_rand_reset.25997328988761211459372806929926667430208539145862969184455683217839135282013
      Line 6029, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 97641662367 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 97641662367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.83948118613297049781792045055437035593613922938766696465773293934183281435689
      Line 5857, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8849679634 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8849679634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_entropy has 1 failures.

    • 32.alert_handler_entropy.83955530557658758565762202340797876122025708135374467137958974830277656951682
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_entropy/latest/run.log

        Job ID: smart:f993591f-217d-4fea-af11-1f170cfabc17
      

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 34.alert_handler_stress_all_with_rand_reset.3707929225854863048482000316971441617859607590943182295369631545945436566639
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7a4844f4-a53c-405e-bc4c-ee781263747d
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 18.alert_handler_sig_int_fail.104355384401020113030995039026544102964549200281478162724318099033265005591578
      Line 910, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 2095902511 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 2095902511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 39.alert_handler_lpg.33927092182726760701523650266643574362564016397130531947301589238613165579005
      Line 63273, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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