ALERT_HANDLER Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.220s	376.489us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.390s	436.924us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.787m	15.464ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.444m	6.351ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.630s	684.495us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.390s	436.924us	20	20	100.00
		alert_handler_csr_aliasing	4.444m	6.351ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.013m	4.830ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.136m	1.439ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.283m	239.576ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.176m	2.047ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.368m	5.193ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.276m	4.806ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.976m	33.619ms	50	50	100.00
V2	lpg	alert_handler_lpg	47.206m	51.097ms	49	50	98.00
		alert_handler_lpg_stub_clk	51.293m	198.386ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.193h	73.000ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	54.530s	1.310ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.340s	48.401us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.900s	17.920us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.780s	1.312ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.780s	1.312ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.220s	376.489us	5	5	100.00
		alert_handler_csr_rw	9.390s	436.924us	20	20	100.00
		alert_handler_csr_aliasing	4.444m	6.351ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.240s	699.377us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.220s	376.489us	5	5	100.00
		alert_handler_csr_rw	9.390s	436.924us	20	20	100.00
		alert_handler_csr_aliasing	4.444m	6.351ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.240s	699.377us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.446m	6.687ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.446m	6.687ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.446m	6.687ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.446m	6.687ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	16.958m	51.350ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
		alert_handler_tl_intg_err	1.405m	1.305ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.405m	1.305ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.446m	6.687ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	58.030s	2.083ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.176m	2.047ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	47.206m	51.097ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.176m	2.047ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.283m	239.576ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.283m	239.576ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.320s	607.599us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	1.913h	64.304ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.73	100.00	100.00	100.00	99.38	99.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 1.alert_handler_stress_all_with_rand_reset.41158424604113603859855091904420018544316975087114300383382406810755870496719
    Line 6196, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4262516351 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4262516351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.40465559894858757754716841839221018995768888620452698592911592785933132848332
    Line 45754, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48861880545 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48861880545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 8.alert_handler_sig_int_fail.1181924039902943413226446926211012303037837331537972299317163230429179087014
    Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  81930563 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 6 [0x6]) reg name: alert_handler_reg_block.classb_state
  UVM_INFO @  81930563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 10.alert_handler_lpg.88259757718956180172562334031504064606092735627901329433777278256412576628466
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_lpg/latest/run.log
```
  Job ID: smart:bf3361ee-4208-4d8d-ad90-121c47b171d3
```

ALERT_HANDLER Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5967df933a`