ALERT_HANDLER Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.590s	447.965us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.770s	163.066us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.363m	9.338ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.439m	19.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.150s	208.689us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.770s	163.066us	20	20	100.00
		alert_handler_csr_aliasing	5.439m	19.106ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.785m	21.108ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.020m	2.203ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.785m	233.248ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.141m	2.193ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.247m	4.192ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.155m	1.268ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.081m	30.708ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.381m	123.808ms	50	50	100.00
		alert_handler_lpg_stub_clk	51.286m	54.148ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.277h	991.487ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.796m	10.723ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.300s	407.431us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.970s	19.104us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.100s	2.509ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.100s	2.509ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.590s	447.965us	5	5	100.00
		alert_handler_csr_rw	9.770s	163.066us	20	20	100.00
		alert_handler_csr_aliasing	5.439m	19.106ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.360s	707.494us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.590s	447.965us	5	5	100.00
		alert_handler_csr_rw	9.770s	163.066us	20	20	100.00
		alert_handler_csr_aliasing	5.439m	19.106ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.360s	707.494us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.375m	5.201ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.375m	5.201ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.375m	5.201ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.375m	5.201ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.280m	17.422ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
		alert_handler_tl_intg_err	1.518m	1.502ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.518m	1.502ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.375m	5.201ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.203m	9.540ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.141m	2.193ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.381m	123.808ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.141m	2.193ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.785m	233.248ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.785m	233.248ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.359m	1.958ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.301h	558.813ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.69	99.99	98.72	100.00	100.00	100.00	99.38	99.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test alert_handler_stress_all_with_rand_reset has 23 failures.

    • 0.alert_handler_stress_all_with_rand_reset.18047461605615657190336751868693795431455831029850331330361374511395440842420
      Line 29155, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121055229806 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 121055229806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.61195487077003787371203169161142210287591279236081246271562551135992990830810
      Line 52097, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89171963695 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 89171963695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

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