ALERT_HANDLER Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 6.700s 141.066us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.950s 491.212us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 7.999m 43.601ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 4.900m 8.543ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 13.800s 185.842us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.950s 491.212us 20 20 100.00
alert_handler_csr_aliasing 4.900m 8.543ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.515m 24.933ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.284m 2.577ms 50 50 100.00
V2 entropy alert_handler_entropy 49.581m 641.841ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.186m 1.136ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.152m 4.020ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.461m 1.235ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 12.362m 17.659ms 50 50 100.00
V2 lpg alert_handler_lpg 53.689m 54.273ms 50 50 100.00
alert_handler_lpg_stub_clk 59.029m 54.679ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.398h 167.663ms 49 50 98.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 51.220s 4.270ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.430s 60.524us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.840s 13.173us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 29.660s 1.432ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 29.660s 1.432ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 6.700s 141.066us 5 5 100.00
alert_handler_csr_rw 10.950s 491.212us 20 20 100.00
alert_handler_csr_aliasing 4.900m 8.543ms 5 5 100.00
alert_handler_same_csr_outstanding 46.770s 10.597ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 6.700s 141.066us 5 5 100.00
alert_handler_csr_rw 10.950s 491.212us 20 20 100.00
alert_handler_csr_aliasing 4.900m 8.543ms 5 5 100.00
alert_handler_same_csr_outstanding 46.770s 10.597ms 20 20 100.00
V2 TOTAL 629 630 99.84
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 7.141m 7.397ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 7.141m 7.397ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 7.141m 7.397ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 7.141m 7.397ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 18.680m 13.727ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
alert_handler_tl_intg_err 1.279m 3.320ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.279m 3.320ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 7.141m 7.397ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.240m 3.346ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.186m 1.136ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 53.689m 54.273ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.186m 1.136ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 49.581m 641.841ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 49.581m 641.841ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 22.350s 1.407ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.801h 405.234ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 830 850 97.65

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 14 93.33
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.64 99.99 98.74 99.97 100.00 100.00 99.38 99.40

Failure Buckets

Past Results