ALERT_HANDLER Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.700s	141.066us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.950s	491.212us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.999m	43.601ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.900m	8.543ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.800s	185.842us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.950s	491.212us	20	20	100.00
		alert_handler_csr_aliasing	4.900m	8.543ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.515m	24.933ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.284m	2.577ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.581m	641.841ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.186m	1.136ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.152m	4.020ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.461m	1.235ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.362m	17.659ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.689m	54.273ms	50	50	100.00
		alert_handler_lpg_stub_clk	59.029m	54.679ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.398h	167.663ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.220s	4.270ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.430s	60.524us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.840s	13.173us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.660s	1.432ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.660s	1.432ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.700s	141.066us	5	5	100.00
		alert_handler_csr_rw	10.950s	491.212us	20	20	100.00
		alert_handler_csr_aliasing	4.900m	8.543ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.770s	10.597ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.700s	141.066us	5	5	100.00
		alert_handler_csr_rw	10.950s	491.212us	20	20	100.00
		alert_handler_csr_aliasing	4.900m	8.543ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.770s	10.597ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.141m	7.397ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.141m	7.397ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.141m	7.397ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.141m	7.397ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.680m	13.727ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
		alert_handler_tl_intg_err	1.279m	3.320ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.279m	3.320ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.141m	7.397ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.240m	3.346ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.186m	1.136ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.689m	54.273ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.186m	1.136ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.581m	641.841ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.581m	641.841ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	22.350s	1.407ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.801h	405.234ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.74	99.97	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
  • Test alert_handler_stress_all_with_rand_reset has 19 failures.

    • 2.alert_handler_stress_all_with_rand_reset.60074954596956032267355464827789804759394458878803620113536574026062425829822
      Line 73426, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 265191786140 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 265191786140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.alert_handler_stress_all_with_rand_reset.47892973087982569712038532220943942961076792990004547911236086460785418024688
      Line 22144, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 93044810930 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 93044810930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:
  • Test alert_handler_stress_all has 1 failures.

    • 0.alert_handler_stress_all.4431272860047801829509609274058115712660643457017851370833415522320779458282
      Line 1814, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 2579941683 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 2579941683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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