ALERT_HANDLER Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.460s	1.883ms	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.670s	483.865us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.856m	8.982ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.369m	4.033ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	10.710s	1.542ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.670s	483.865us	20	20	100.00
		alert_handler_csr_aliasing	4.369m	4.033ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.568m	14.605ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.183m	4.463ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.251m	199.761ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.198m	1.169ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.187m	20.135ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.281m	1.281ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.516m	16.738ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.976m	231.398ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.226m	277.676ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.166h	77.159ms	47	50	94.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	36.260s	2.992ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.070s	55.070us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.750s	12.272us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.690s	4.718ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.690s	4.718ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.460s	1.883ms	5	5	100.00
		alert_handler_csr_rw	9.670s	483.865us	20	20	100.00
		alert_handler_csr_aliasing	4.369m	4.033ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.950s	3.862ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.460s	1.883ms	5	5	100.00
		alert_handler_csr_rw	9.670s	483.865us	20	20	100.00
		alert_handler_csr_aliasing	4.369m	4.033ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.950s	3.862ms	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.083m	5.025ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.083m	5.025ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.083m	5.025ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.083m	5.025ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.396m	19.278ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
		alert_handler_tl_intg_err	1.446m	4.819ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.446m	4.819ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.083m	5.025ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.116m	4.575ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.198m	1.169ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.976m	231.398ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.198m	1.169ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.251m	199.761ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.251m	199.761ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	29.930s	609.588us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.190h	70.932ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.71	100.00	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test alert_handler_stress_all_with_rand_reset has 14 failures.
  - 2.alert_handler_stress_all_with_rand_reset.37824510772816440082789795076711248767192003448027809638630547607444548061924
    Line 1963, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1726074226 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1726074226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.alert_handler_stress_all_with_rand_reset.3506736791071140401508842308811130849267596829376378615842700610979252110804
    Line 12436, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75752249609 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 75752249609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 8.alert_handler_stress_all.32144564187267228944041434892235266035287272660401637701768359036368408577626
    Line 992, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 352022700 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 352022700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 21.alert_handler_sig_int_fail.33931632495124482449383242967399083207135829934608387220183245768328716756372
    Line 336, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 586242343 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 586242343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 29.alert_handler_stress_all.22376854336430140187949858655358335959202532475551109639762943569688460002228
    Line 54164, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 61366951934 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (91 [0x5b] vs 684 [0x2ac])
  UVM_INFO @ 61366951934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 41.alert_handler_stress_all_with_rand_reset.98514504579485312047543603620818727493050186596901634080598038745419279036846
    Line 4940, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14918644459 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 14918644459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 43.alert_handler_stress_all.8537357939433851610734289770207572344152422132492815078195101444213884579016
    Line 51794, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 109901695237 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 109901695237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a04e34f557`