ALERT_HANDLER Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.550s	110.942us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.500s	248.551us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.867m	95.138ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.142m	13.680ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.780s	925.579us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.500s	248.551us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	13.680ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.362m	6.088ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.296m	2.388ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.879m	420.479ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.087m	4.276ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.308m	1.268ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.314m	4.832ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.721m	61.218ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.402m	209.398ms	49	50	98.00
		alert_handler_lpg_stub_clk	53.379m	54.523ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.172h	276.091ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.008m	5.408ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.830s	218.564us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.930s	23.277us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	19.830s	512.417us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	19.830s	512.417us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.550s	110.942us	5	5	100.00
		alert_handler_csr_rw	10.500s	248.551us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	13.680ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.080s	2.786ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.550s	110.942us	5	5	100.00
		alert_handler_csr_rw	10.500s	248.551us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	13.680ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.080s	2.786ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.630m	42.047ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.630m	42.047ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.630m	42.047ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.630m	42.047ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.777m	16.607ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
		alert_handler_tl_intg_err	1.227m	3.701ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.227m	3.701ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.630m	42.047ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.264m	5.078ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.087m	4.276ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.402m	209.398ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.087m	4.276ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.879m	420.479ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.879m	420.479ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.720s	1.021ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.131h	141.429ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.99	98.74	100.00	100.00	100.00	99.38	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test alert_handler_stress_all_with_rand_reset has 14 failures.
  - 4.alert_handler_stress_all_with_rand_reset.44265532177867190489206261247012751188173422652125462924855140159430966735993
    Line 35544, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34651102770 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34651102770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.alert_handler_stress_all_with_rand_reset.88412860590611864781833269691499392123075398203884117618914839877451447519366
    Line 13493, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25720656050 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25720656050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 22.alert_handler_stress_all_with_rand_reset.71842528701425009549593829064919401307703374243636083161792819311835512542674
    Line 116393, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 147510181566 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 147510181566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.alert_handler_stress_all_with_rand_reset.32335732691636280946301238367900388629801311155944807869035143425092942593486
    Line 46151, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127973298890 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 127973298890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 10.alert_handler_lpg.64187241336715706892498367089780871077782845954444368499256212708640606396438
    Line 72106, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_lpg/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 20.alert_handler_stress_all_with_rand_reset.104807951852887003903287776278766909947880958165319354718774213724057361444816
    Line 42436, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9695800622 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 9695800622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 24.alert_handler_stress_all_with_rand_reset.3632890221244724888849226898984617607686374952070778840132981925697570424795
    Line 25497, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6195450237 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 6195450237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`