ALERT_HANDLER Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 9.280s 102.428us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.530s 252.056us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 7.124m 7.734ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 2.914m 1.134ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 13.820s 1.077ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.530s 252.056us 20 20 100.00
alert_handler_csr_aliasing 2.914m 1.134ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.794m 25.656ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.148m 10.992ms 50 50 100.00
V2 entropy alert_handler_entropy 51.570m 179.789ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.125m 4.586ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.090m 4.503ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.149m 1.834ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 10.456m 31.960ms 50 50 100.00
V2 lpg alert_handler_lpg 56.107m 227.009ms 50 50 100.00
alert_handler_lpg_stub_clk 55.515m 261.943ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.180h 76.658ms 50 50 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 59.910s 5.554ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.750s 58.894us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.740s 10.512us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 28.070s 1.388ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 28.070s 1.388ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 9.280s 102.428us 5 5 100.00
alert_handler_csr_rw 10.530s 252.056us 20 20 100.00
alert_handler_csr_aliasing 2.914m 1.134ms 5 5 100.00
alert_handler_same_csr_outstanding 54.780s 11.264ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 9.280s 102.428us 5 5 100.00
alert_handler_csr_rw 10.530s 252.056us 20 20 100.00
alert_handler_csr_aliasing 2.914m 1.134ms 5 5 100.00
alert_handler_same_csr_outstanding 54.780s 11.264ms 20 20 100.00
V2 TOTAL 630 630 100.00
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 6.176m 5.333ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 6.176m 5.333ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 6.176m 5.333ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 6.176m 5.333ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 17.962m 73.297ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
alert_handler_tl_intg_err 1.496m 2.420ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.496m 2.420ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 6.176m 5.333ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.202m 17.064ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.125m 4.586ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 56.107m 227.009ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.125m 4.586ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 51.570m 179.789ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 51.570m 179.789ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 3.220m 5.181ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.021h 81.075ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 829 850 97.53

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 15 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.64 99.99 98.68 100.00 100.00 100.00 99.38 99.44

Failure Buckets

Past Results