ALERT_HANDLER Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 54.260s 946.787us 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 8.790s 102.472us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.150s 130.703us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 6.775m 10.961ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 5.562m 18.797ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 11.550s 149.254us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.150s 130.703us 20 20 100.00
alert_handler_csr_aliasing 5.562m 18.797ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 4.546m 21.448ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.136m 4.473ms 50 50 100.00
V2 entropy alert_handler_entropy 58.066m 220.330ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.152m 4.547ms 49 50 98.00
V2 clk_skew alert_handler_smoke 54.260s 946.787us 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.288m 5.225ms 50 50 100.00
V2 random_classes alert_handler_random_classes 57.970s 824.633us 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 11.140m 65.076ms 50 50 100.00
V2 lpg alert_handler_lpg 57.039m 242.467ms 49 50 98.00
alert_handler_lpg_stub_clk 46.255m 58.423ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.003h 403.453ms 49 50 98.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 54.960s 2.658ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.010s 54.348us 20 20 100.00
V2 intr_test alert_handler_intr_test 3.610s 69.145us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 20.160s 1.202ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 20.160s 1.202ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 8.790s 102.472us 5 5 100.00
alert_handler_csr_rw 10.150s 130.703us 20 20 100.00
alert_handler_csr_aliasing 5.562m 18.797ms 5 5 100.00
alert_handler_same_csr_outstanding 53.040s 2.797ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 8.790s 102.472us 5 5 100.00
alert_handler_csr_rw 10.150s 130.703us 20 20 100.00
alert_handler_csr_aliasing 5.562m 18.797ms 5 5 100.00
alert_handler_same_csr_outstanding 53.040s 2.797ms 20 20 100.00
V2 TOTAL 627 630 99.52
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 6.615m 5.554ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 6.615m 5.554ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 6.615m 5.554ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 6.615m 5.554ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 18.758m 34.092ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
alert_handler_tl_intg_err 1.364m 2.365ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.364m 2.365ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 6.615m 5.554ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 54.260s 946.787us 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 54.260s 946.787us 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 54.260s 946.787us 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 54.260s 946.787us 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.152m 4.547ms 49 50 98.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 57.039m 242.467ms 49 50 98.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.152m 4.547ms 49 50 98.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 58.066m 220.330ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 58.066m 220.330ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 25.880s 469.288us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.675h 106.868ms 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 827 850 97.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 12 80.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.66 99.99 98.67 100.00 100.00 100.00 99.38 99.56

Failure Buckets

Past Results