ALERT_HANDLER Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.040s	144.428us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.330s	247.005us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.606m	23.704ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.132m	13.481ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.400s	162.006us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.330s	247.005us	20	20	100.00
		alert_handler_csr_aliasing	4.132m	13.481ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.587m	23.532ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.142m	1.236ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.540m	104.539ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.137m	4.946ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.055m	1.027ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.154m	7.280ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.342m	29.986ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.849m	109.420ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.585m	55.271ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.098h	243.361ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	50.310s	5.028ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.940s	229.442us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.530s	37.882us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.330s	371.658us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.330s	371.658us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.040s	144.428us	5	5	100.00
		alert_handler_csr_rw	9.330s	247.005us	20	20	100.00
		alert_handler_csr_aliasing	4.132m	13.481ms	5	5	100.00
		alert_handler_same_csr_outstanding	39.710s	3.832ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.040s	144.428us	5	5	100.00
		alert_handler_csr_rw	9.330s	247.005us	20	20	100.00
		alert_handler_csr_aliasing	4.132m	13.481ms	5	5	100.00
		alert_handler_same_csr_outstanding	39.710s	3.832ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.829m	6.626ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.829m	6.626ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.829m	6.626ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.829m	6.626ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.253m	33.640ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
		alert_handler_tl_intg_err	1.205m	2.167ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.205m	2.167ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.829m	6.626ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.197m	1.282ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.137m	4.946ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.849m	109.420ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.137m	4.946ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.540m	104.539ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.540m	104.539ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	44.690s	1.067ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.658h	266.837ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.99	98.64	99.97	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test alert_handler_stress_all_with_rand_reset has 15 failures.
  - 12.alert_handler_stress_all_with_rand_reset.29698170744617049250091142487431743778125561448384004195962065694720892729294
    Line 442, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107545597 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107545597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.alert_handler_stress_all_with_rand_reset.13776289879472286513047499818091623436142950495246911473229699269262731352831
    Line 10788, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59495784838 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59495784838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 4.alert_handler_sig_int_fail.38047126790124622568428968852302165431748818487048061445662740922071624809611
    Line 828, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 1066267627 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1066267627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 10.alert_handler_stress_all_with_rand_reset.111385816010770349895421588389451250048177291309073182103198919364492308058948
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:89942d86-2f3f-42e3-8f3c-0f47cfa47c40
```
UVM_ERROR (cip_base_vseq.sv:758) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 44.alert_handler_stress_all_with_rand_reset.42345568646695147331415472847307849871032047782766769747979996747280169223915
    Line 37025, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39368696161 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 39368696161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`