ALERT_HANDLER Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.520s	497.115us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.050s	133.105us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.822m	15.141ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.175m	5.019ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.670s	680.900us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.050s	133.105us	20	20	100.00
		alert_handler_csr_aliasing	4.175m	5.019ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.731m	11.757ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.390m	5.735ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.196m	232.319ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.267m	4.538ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.272m	1.281ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.179m	2.174ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.986m	33.187ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.876m	121.519ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.967m	597.939ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.086h	591.451ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.500s	5.251ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.570s	91.034us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.010s	25.093us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.980s	1.729ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.980s	1.729ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.520s	497.115us	5	5	100.00
		alert_handler_csr_rw	11.050s	133.105us	20	20	100.00
		alert_handler_csr_aliasing	4.175m	5.019ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.290s	3.253ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.520s	497.115us	5	5	100.00
		alert_handler_csr_rw	11.050s	133.105us	20	20	100.00
		alert_handler_csr_aliasing	4.175m	5.019ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.290s	3.253ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.014m	4.491ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.014m	4.491ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.014m	4.491ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.014m	4.491ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.525m	18.328ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
		alert_handler_tl_intg_err	1.438m	2.494ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.438m	2.494ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.014m	4.491ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.233m	1.162ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.267m	4.538ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.876m	121.519ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.267m	4.538ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.196m	232.319ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.196m	232.319ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.940s	634.667us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.796h	397.876ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.72	100.00	100.00	100.00	99.30	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 5.alert_handler_stress_all_with_rand_reset.59249022040565144997703647886479655405745156976465508080015184727900543909359
      Line 13348, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50510545129 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50510545129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.alert_handler_stress_all_with_rand_reset.36283821945967849298714015616554360900994960863948351443432462898251907879509
      Line 12747, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54038641231 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 54038641231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 22.alert_handler_stress_all_with_rand_reset.83177100703908992881097842423260274074873141919262576798490258599596369784174
      Line 1250, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4327649546 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 4327649546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.07.20_10.09.03
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