ALERT_HANDLER Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.720s	131.756us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.390s	568.942us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.543m	25.905ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.542m	12.164ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	10.690s	62.009us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.390s	568.942us	20	20	100.00
		alert_handler_csr_aliasing	4.542m	12.164ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.984m	5.715ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.155m	2.405ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.378m	220.113ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.135m	11.108ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.087m	2.017ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.379m	1.272ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.989m	34.918ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.691m	56.709ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.994m	118.624ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.181h	316.535ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.252m	6.934ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.760s	124.364us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.950s	19.302us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.610s	758.386us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.610s	758.386us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.720s	131.756us	5	5	100.00
		alert_handler_csr_rw	9.390s	568.942us	20	20	100.00
		alert_handler_csr_aliasing	4.542m	12.164ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.130s	670.415us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.720s	131.756us	5	5	100.00
		alert_handler_csr_rw	9.390s	568.942us	20	20	100.00
		alert_handler_csr_aliasing	4.542m	12.164ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.130s	670.415us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.362m	5.990ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.362m	5.990ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.362m	5.990ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.362m	5.990ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.155m	15.212ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
		alert_handler_tl_intg_err	1.515m	5.170ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.515m	5.170ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.362m	5.990ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.237m	4.689ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.135m	11.108ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.691m	56.709ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.135m	11.108ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.378m	220.113ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.378m	220.113ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.670s	622.153us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.493h	344.354ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.74	100.00	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 1.alert_handler_stress_all_with_rand_reset.70083546090068386408887331038116767524688438946461800436087967948989777030405
      Line 115798, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 433952728918 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 433952728918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.10389736747644627606461246519564276302488879263524527137710684944100744560913
      Line 46483, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 136454165367 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 136454165367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
  • Test alert_handler_sig_int_fail has 1 failures.

    • 49.alert_handler_sig_int_fail.16854924213980813962037353846508351105488800588447368476877245946985691362646
      Line 991, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 525650767 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 525650767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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