ALERT_HANDLER Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.070s	458.851us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.910s	185.975us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.501m	8.555ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.716m	30.085ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.230s	156.889us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.910s	185.975us	20	20	100.00
		alert_handler_csr_aliasing	5.716m	30.085ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.515m	5.209ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.103m	1.838ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.660m	57.757ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.038m	4.394ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.180m	1.368ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.369m	5.486ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.735m	54.548ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.078m	171.153ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.578m	119.078ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.064h	130.652ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.026m	5.496ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.240s	59.879us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.850s	15.429us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.150s	1.413ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.150s	1.413ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.070s	458.851us	5	5	100.00
		alert_handler_csr_rw	9.910s	185.975us	20	20	100.00
		alert_handler_csr_aliasing	5.716m	30.085ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.080s	12.947ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.070s	458.851us	5	5	100.00
		alert_handler_csr_rw	9.910s	185.975us	20	20	100.00
		alert_handler_csr_aliasing	5.716m	30.085ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.080s	12.947ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.627m	5.401ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.627m	5.401ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.627m	5.401ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.627m	5.401ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.021m	31.170ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
		alert_handler_tl_intg_err	1.402m	4.401ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.402m	4.401ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.627m	5.401ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.070m	6.105ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.038m	4.394ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.078m	171.153ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.038m	4.394ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.660m	57.757ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.660m	57.757ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.310s	539.498us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.240h	130.262ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			840	850	98.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.70	100.00	100.00	100.00	99.38	99.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test alert_handler_stress_all_with_rand_reset has 9 failures.
  - 7.alert_handler_stress_all_with_rand_reset.107169983330393350115388679295212003812038025351042111159260186980099167480829
    Line 15991, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11255414411 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11255414411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.alert_handler_stress_all_with_rand_reset.11604853983377651120853298689999104391723030538736562198069013926583999768946
    Line 352, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 101595331 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 101595331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 37.alert_handler_sig_int_fail.107562740757527171556758506735451585742246569024234319477133139328777850909576
    Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 146535178 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 146535178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e0219a2c5`