ALERT_HANDLER Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.090s	121.892us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.660s	124.200us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.762m	29.598ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.139m	66.750ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.600s	959.063us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.660s	124.200us	20	20	100.00
		alert_handler_csr_aliasing	4.139m	66.750ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.273m	5.404ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.391m	5.198ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.970m	54.450ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.175m	1.385ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.058m	1.133ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.245m	1.215ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.237m	15.078ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.269m	328.926ms	49	50	98.00
		alert_handler_lpg_stub_clk	52.336m	49.502ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.017h	61.379ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.330m	7.705ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	5.060s	183.476us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.920s	17.909us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.690s	1.252ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.690s	1.252ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.090s	121.892us	5	5	100.00
		alert_handler_csr_rw	9.660s	124.200us	20	20	100.00
		alert_handler_csr_aliasing	4.139m	66.750ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.560s	1.398ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.090s	121.892us	5	5	100.00
		alert_handler_csr_rw	9.660s	124.200us	20	20	100.00
		alert_handler_csr_aliasing	4.139m	66.750ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.560s	1.398ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.353m	5.653ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.353m	5.653ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.353m	5.653ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.353m	5.653ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.325m	15.434ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
		alert_handler_tl_intg_err	1.353m	2.345ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.353m	2.345ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.353m	5.653ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.212m	2.073ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.175m	1.385ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.269m	328.926ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.175m	1.385ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.970m	54.450ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.970m	54.450ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.730s	549.541us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.670h	263.455ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.76	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 0.alert_handler_stress_all_with_rand_reset.42494257526726349689375776427648543585200422864916040015307774364409911230571
      Line 4870, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8763943630 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8763943630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.15773472797103913135988697385469588601658397057514317285031699865666443012565
      Line 67812, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50036544187 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50036544187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test alert_handler_lpg has 1 failures.

    • 27.alert_handler_lpg.85308939104255441769829039554569082560507067527234831223076903576473410124611
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_lpg/latest/run.log

        Job ID: smart:c60ff514-9e36-4081-a0cf-17f7a995e671
      

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