ALERT_HANDLER Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.240s	101.250us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.390s	177.688us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.634m	40.684ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.288m	18.335ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.390s	741.923us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.390s	177.688us	20	20	100.00
		alert_handler_csr_aliasing	5.288m	18.335ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.042m	44.985ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.327m	5.072ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.000m	88.610ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.087m	1.717ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.115m	7.640ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.086m	2.935ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.308m	59.221ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.848m	55.441ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.951m	217.062ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.118h	64.118ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.048m	2.942ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.250s	50.469us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.220s	27.319us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.650s	1.251ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.650s	1.251ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.240s	101.250us	5	5	100.00
		alert_handler_csr_rw	9.390s	177.688us	20	20	100.00
		alert_handler_csr_aliasing	5.288m	18.335ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.640s	2.357ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.240s	101.250us	5	5	100.00
		alert_handler_csr_rw	9.390s	177.688us	20	20	100.00
		alert_handler_csr_aliasing	5.288m	18.335ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.640s	2.357ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.971m	5.152ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.971m	5.152ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.971m	5.152ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.971m	5.152ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.978m	92.742ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
		alert_handler_tl_intg_err	1.278m	1.405ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.278m	1.405ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.971m	5.152ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.207m	4.696ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.087m	1.717ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.848m	55.441ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.087m	1.717ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.000m	88.610ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.000m	88.610ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.790s	619.931us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.645h	368.877ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.71	100.00	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

  • Test alert_handler_stress_all_with_rand_reset has 13 failures.

    • 0.alert_handler_stress_all_with_rand_reset.42231644054011147250944228149507873790932722069243865877819195334211349534731
      Line 87846, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 233684181519 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 233684181519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.57219317977739722182485016360520785644993840105483463349170981128825493738581
      Line 80385, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 310813473282 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 310813473282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (cip_base_vseq.sv:758) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 11.alert_handler_stress_all_with_rand_reset.70444522322522080826157547279279384699000815527477902944306608388697507764939
      Line 128748, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36383493753 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 36383493753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 39.alert_handler_sig_int_fail.61304298531886558617767437623446827342475292640729092490268621896242710406189
      Line 910, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 148924580 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (257 [0x101] vs 5 [0x5])
        UVM_INFO @ 148924580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:500) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 42.alert_handler_stress_all_with_rand_reset.6594102222167422687600480098404779848804753626188848743184576167854664968159
      Line 2002, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4533133411 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 4533133411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.24_08.31.54
• 2024.07.23_09.03.35
• 2024.07.22_09.02.46
• 2024.07.21_08.44.12
• 2024.07.20_10.09.03
• 2024.07.19_09.08.34