ALERT_HANDLER Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.780s	421.969us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.020s	110.103us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.874m	23.784ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.706m	3.415ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.970s	556.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.020s	110.103us	20	20	100.00
		alert_handler_csr_aliasing	4.706m	3.415ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.838m	15.199ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.189m	3.136ms	50	50	100.00
V2	entropy	alert_handler_entropy	45.347m	55.553ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.191m	1.122ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.117m	1.078ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.233m	10.491ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.889m	16.392ms	49	50	98.00
V2	lpg	alert_handler_lpg	46.789m	88.126ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.848m	114.316ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.263h	309.101ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	59.800s	14.229ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	5.010s	56.709us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.090s	20.810us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.680s	5.653ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.680s	5.653ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.780s	421.969us	5	5	100.00
		alert_handler_csr_rw	8.020s	110.103us	20	20	100.00
		alert_handler_csr_aliasing	4.706m	3.415ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.720s	1.380ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.780s	421.969us	5	5	100.00
		alert_handler_csr_rw	8.020s	110.103us	20	20	100.00
		alert_handler_csr_aliasing	4.706m	3.415ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.720s	1.380ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.074m	6.930ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.074m	6.930ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.074m	6.930ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.074m	6.930ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.344m	71.238ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
		alert_handler_tl_intg_err	1.353m	1.221ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.353m	1.221ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.074m	6.930ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.301m	4.882ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.191m	1.122ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	46.789m	88.126ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.191m	1.122ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	45.347m	55.553ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	45.347m	55.553ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.820s	852.777us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.641h	515.239ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.99	98.74	97.09	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test alert_handler_stress_all_with_rand_reset has 16 failures.

    • 1.alert_handler_stress_all_with_rand_reset.92660095434342727902508784805079902596266053851258247287822531742573444938139
      Line 40644, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6988606372 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6988606372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.93818909338422184776330296844530814187997358490633509793444556139662599197808
      Line 18564, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 392966930383 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 392966930383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_entropy has 1 failures.

    • 26.alert_handler_entropy.53220899676997437159777556936942496454344393060387296095796345175560363652095
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_entropy/latest/run.log

        Job ID: smart:e933a6ee-54ff-4dac-8567-484a950f1e32
      

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 30.alert_handler_stress_all_with_rand_reset.53909396616348850495677743061059827785041107699934490383850671486883736423912
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:658a796b-219b-4474-b215-2fa93c96dae4
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 18.alert_handler_ping_timeout.36302833309739962330873826929702892414897466128178541706450300328333078693530
      Line 1008, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 3126705241 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 7 [0x7]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @ 3126705241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.07.25_08.52.25
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• 2024.07.23_09.03.35
• 2024.07.22_09.02.46
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