ALERT_HANDLER Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	5.460s	222.042us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.380s	132.598us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.757m	23.783ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.273m	5.946ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.760s	628.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.380s	132.598us	20	20	100.00
		alert_handler_csr_aliasing	4.273m	5.946ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.044m	6.246ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.223m	2.110ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.379m	637.906ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.065m	1.043ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.122m	8.103ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.196m	2.246ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.066m	37.974ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.356m	118.848ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.762m	221.455ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.074h	136.123ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	53.600s	2.675ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.270s	46.561us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.780s	16.882us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.790s	2.347ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.790s	2.347ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	5.460s	222.042us	5	5	100.00
		alert_handler_csr_rw	10.380s	132.598us	20	20	100.00
		alert_handler_csr_aliasing	4.273m	5.946ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.500s	1.365ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	5.460s	222.042us	5	5	100.00
		alert_handler_csr_rw	10.380s	132.598us	20	20	100.00
		alert_handler_csr_aliasing	4.273m	5.946ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.500s	1.365ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.512m	4.628ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.512m	4.628ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.512m	4.628ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.512m	4.628ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.563m	69.142ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
		alert_handler_tl_intg_err	50.100s	306.189us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	50.100s	306.189us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.512m	4.628ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.026m	825.490us	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.065m	1.043ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.356m	118.848ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.065m	1.043ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.379m	637.906ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.379m	637.906ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	22.980s	1.717ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.181h	294.839ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.72	97.09	100.00	100.00	99.38	99.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 6.alert_handler_stress_all_with_rand_reset.89735070085947241469420360710042959376709372713152480003797199521408048762001
    Line 49325, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50899137459 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50899137459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.alert_handler_stress_all_with_rand_reset.46117848695709259956884964781905112131904387081411572369665970845373916497844
    Line 12164, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17048254359 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17048254359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 2 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 19.alert_handler_sig_int_fail.68000756684766046538208601727403971795456322618370212200124738006585297460105
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 123301436 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
  UVM_INFO @ 123301436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 42.alert_handler_stress_all_with_rand_reset.89732718361121239426957207933403424438347116738256234119501461035134686863144
    Line 72438, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 487937696249 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
  UVM_INFO @ 487937696249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 0.alert_handler_stress_all.70169399680352627032688057734654731267939281940135941456162671382279176759380
    Line 45959, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 54809196496 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 54809196496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4877b481e8`