ALERT_HANDLER Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.180s	515.801us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.190s	496.265us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.383m	38.887ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.468m	5.797ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.530s	2.477ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.190s	496.265us	20	20	100.00
		alert_handler_csr_aliasing	5.468m	5.797ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.554m	5.853ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.194m	4.256ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.032m	104.905ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.438m	1.359ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.263m	4.398ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.179m	1.067ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.922m	17.104ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.490m	273.867ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.770m	239.950ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.046h	62.565ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	40.100s	887.095us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.580s	47.465us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.070s	23.089us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	16.670s	271.493us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	16.670s	271.493us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.180s	515.801us	5	5	100.00
		alert_handler_csr_rw	10.190s	496.265us	20	20	100.00
		alert_handler_csr_aliasing	5.468m	5.797ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.240s	2.760ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.180s	515.801us	5	5	100.00
		alert_handler_csr_rw	10.190s	496.265us	20	20	100.00
		alert_handler_csr_aliasing	5.468m	5.797ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.240s	2.760ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.085m	20.750ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.085m	20.750ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.085m	20.750ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.085m	20.750ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.240m	32.176ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
		alert_handler_tl_intg_err	1.299m	4.522ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.299m	4.522ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.085m	20.750ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.262m	9.477ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.438m	1.359ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.490m	273.867ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.438m	1.359ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.032m	104.905ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.032m	104.905ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.230m	1.802ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.746h	387.012ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.65	97.09	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test alert_handler_stress_all_with_rand_reset has 19 failures.
  - 1.alert_handler_stress_all_with_rand_reset.6832959531751163893542808239915154382498879000561843222507223726866112949913
    Line 42852, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118818789199 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 118818789199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.73849600148396513004878018029377141262128758584281173772130726859948269946484
    Line 18646, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 98798473400 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 98798473400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 31.alert_handler_stress_all_with_rand_reset.90138534838413794805130260038318388581734953333208732915272799542883705818530
    Line 501, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 547309697 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
  UVM_INFO @ 547309697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 37.alert_handler_sig_int_fail.29795502728509437852976199846118074615258576024575142778642163589756285164675
    Line 745, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 1414224822 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1414224822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 43.alert_handler_lpg.99863487921653122288654770786965257877840068371873018922086423054145875241848
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_lpg/latest/run.log
```
  Job ID: smart:54296df5-9ce7-403e-b01b-70461d84b62e
```

ALERT_HANDLER Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`