ALERT_HANDLER Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.880s	431.277us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.520s	459.719us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.758m	5.720ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.977m	5.506ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.360s	151.440us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.520s	459.719us	20	20	100.00
		alert_handler_csr_aliasing	4.977m	5.506ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.440m	21.244ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.311m	1.342ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.952m	112.896ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.281m	4.892ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.391m	4.893ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.305m	4.597ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.200m	49.926ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.627m	57.549ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.240m	59.154ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.252h	72.971ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	30.850s	6.872ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.640s	190.059us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.750s	10.713us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.840s	1.232ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.840s	1.232ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.880s	431.277us	5	5	100.00
		alert_handler_csr_rw	9.520s	459.719us	20	20	100.00
		alert_handler_csr_aliasing	4.977m	5.506ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.600s	2.806ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.880s	431.277us	5	5	100.00
		alert_handler_csr_rw	9.520s	459.719us	20	20	100.00
		alert_handler_csr_aliasing	4.977m	5.506ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.600s	2.806ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.730m	52.464ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.730m	52.464ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.730m	52.464ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.730m	52.464ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.857m	16.871ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
		alert_handler_tl_intg_err	1.325m	1.761ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.325m	1.761ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.730m	52.464ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.331m	1.284ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.281m	4.892ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.627m	57.549ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.281m	4.892ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.952m	112.896ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.952m	112.896ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	38.700s	882.604us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.826h	1.039s	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.71	97.09	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 2.alert_handler_stress_all_with_rand_reset.69042750971085270157957935256190953322836293104459557351339416917613172108543
    Line 2897, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1910816656 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1910816656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.alert_handler_stress_all_with_rand_reset.114645933120784472470096815767122440922408161658362684465647469444104014843647
    Line 56872, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 208612238878 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 208612238878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:500) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 24.alert_handler_sig_int_fail.12551301252103624400223679473169538796920812198376141982203891713237807876144
    Line 419, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  79212392 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (8 [0x8] vs 0 [0x0])
  UVM_INFO @  79212392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 31.alert_handler_stress_all_with_rand_reset.69505846865883913557188860990955072258854674141063576556856541060101590440829
    Line 10623, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2896716321 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 2896716321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 16.alert_handler_lpg_stub_clk.15728592500114668702295866920664472983134953664251601056661944074762188484157
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:3c8f902c-c0ee-4358-ab3f-a14fca4e658d
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 19.alert_handler_stress_all_with_rand_reset.86326349290812328029991152364827817200199492853342125055521308085334772707315
    Line 22011, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89464503809 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 89464503809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`