ALERT_HANDLER Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.980s	122.546us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.080s	187.782us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	10.016m	77.885ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.337m	1.116ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.060s	189.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.080s	187.782us	20	20	100.00
		alert_handler_csr_aliasing	2.337m	1.116ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.375m	12.031ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.215m	1.558ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.843m	449.594ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.057m	2.226ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.236m	9.113ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.205m	5.413ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.125m	63.996ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.122m	166.578ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.846m	248.263ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.351h	306.687ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.860s	5.559ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.120s	49.886us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.740s	16.737us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.770s	4.551ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.770s	4.551ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.980s	122.546us	5	5	100.00
		alert_handler_csr_rw	9.080s	187.782us	20	20	100.00
		alert_handler_csr_aliasing	2.337m	1.116ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.790s	2.958ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.980s	122.546us	5	5	100.00
		alert_handler_csr_rw	9.080s	187.782us	20	20	100.00
		alert_handler_csr_aliasing	2.337m	1.116ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.790s	2.958ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.698m	5.057ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.698m	5.057ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.698m	5.057ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.698m	5.057ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.161m	91.544ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
		alert_handler_tl_intg_err	1.112m	4.413ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.112m	4.413ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.698m	5.057ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.136m	1.153ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.057m	2.226ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.122m	166.578ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.057m	2.226ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.843m	449.594ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.843m	449.594ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.550s	1.720ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.218h	79.542ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	99.99	98.63	97.09	100.00	100.00	99.38	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
  • Test alert_handler_stress_all_with_rand_reset has 21 failures.

    • 0.alert_handler_stress_all_with_rand_reset.46466258497394774887479339037671478159346109960616126501501329717511629535599
      Line 4987, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5235338296 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5235338296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.34959197387860810522431643971249624738304302773203046995481481997524392548085
      Line 28530, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89192273037 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 89192273037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

Past Results

• Latest
• lint
• 2024.07.29_08.06.46
• 2024.07.28_11.06.44
• 2024.07.27_09.59.12
• 2024.07.26_09.20.20
• 2024.07.25_08.52.25
• 2024.07.24_08.31.54