ALERT_HANDLER Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.520s	362.617us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.960s	362.944us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.156m	8.644ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.390m	8.941ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.980s	715.106us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.960s	362.944us	20	20	100.00
		alert_handler_csr_aliasing	5.390m	8.941ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.328m	5.033ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.158m	2.849ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.431m	343.680ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.406m	1.274ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.127m	4.383ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.110m	4.811ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.028m	33.021ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.121m	860.759ms	49	50	98.00
		alert_handler_lpg_stub_clk	59.250m	228.635ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.180h	141.185ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.079m	6.201ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.500s	62.425us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.750s	9.922us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.440s	311.059us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.440s	311.059us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.520s	362.617us	5	5	100.00
		alert_handler_csr_rw	9.960s	362.944us	20	20	100.00
		alert_handler_csr_aliasing	5.390m	8.941ms	5	5	100.00
		alert_handler_same_csr_outstanding	56.930s	5.726ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.520s	362.617us	5	5	100.00
		alert_handler_csr_rw	9.960s	362.944us	20	20	100.00
		alert_handler_csr_aliasing	5.390m	8.941ms	5	5	100.00
		alert_handler_same_csr_outstanding	56.930s	5.726ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.702m	5.445ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.702m	5.445ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.702m	5.445ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.702m	5.445ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.078m	95.858ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
		alert_handler_tl_intg_err	1.542m	5.176ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.542m	5.176ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.702m	5.445ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.281m	4.396ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.406m	1.274ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.121m	860.759ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.406m	1.274ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.431m	343.680ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.431m	343.680ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.820s	605.901us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.496h	102.369ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.64	99.99	98.66	92.86	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 3.alert_handler_stress_all_with_rand_reset.12442900128551903083289755759867724496940743461044206155578254080482049041671
      Line 110119, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 483738376101 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 483738376101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.86249132133173791823137231388093293950039630874339088349367660993259426720262
      Line 23679, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26042572713 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26042572713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_entropy has 1 failures.

    • 9.alert_handler_entropy.83830902363172315485577866985135627423476195849354453809163571617444325936267
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_entropy/latest/run.log

        Job ID: smart:6ed6b54d-2365-4fe0-9bbc-08a4a11e7d9c
      

  • Test alert_handler_lpg has 1 failures.

    • 25.alert_handler_lpg.68277449392691320423629601912129550446868172238785706948122271948456457931924
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_lpg/latest/run.log

        Job ID: smart:5712bd55-2574-4fe6-b9b5-9e38e0e47d48
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 46.alert_handler_stress_all_with_rand_reset.45582009773610955962877332440671839024681253013965564471198954939759088844543
      Line 161600, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39901136903 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 7 [0x7]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 39901136903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 47.alert_handler_sig_int_fail.50273939805762726665511170753223330336395020797275633945873213877792660647306
      Line 419, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  31162854 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @  31162854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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