ALERT_HANDLER Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.440s	537.663us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.810s	489.191us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.104m	22.787ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.796m	2.273ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.750s	61.227us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.810s	489.191us	20	20	100.00
		alert_handler_csr_aliasing	2.796m	2.273ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.070m	5.918ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.220m	2.577ms	50	50	100.00
V2	entropy	alert_handler_entropy	52.480m	47.564ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.149m	1.172ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.241m	1.307ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.358m	1.267ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.052m	61.921ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.472m	206.617ms	46	50	92.00
		alert_handler_lpg_stub_clk	52.390m	50.635ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.163h	141.570ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.299m	7.000ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.420s	58.977us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.010s	23.188us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.520s	422.264us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.520s	422.264us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.440s	537.663us	5	5	100.00
		alert_handler_csr_rw	9.810s	489.191us	20	20	100.00
		alert_handler_csr_aliasing	2.796m	2.273ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.820s	715.121us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.440s	537.663us	5	5	100.00
		alert_handler_csr_rw	9.810s	489.191us	20	20	100.00
		alert_handler_csr_aliasing	2.796m	2.273ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.820s	715.121us	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.785m	23.480ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.785m	23.480ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.785m	23.480ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.785m	23.480ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.894m	15.495ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
		alert_handler_tl_intg_err	1.130m	6.141ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.130m	6.141ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.785m	23.480ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.192m	1.329ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.149m	1.172ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.472m	206.617ms	46	50	92.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.149m	1.172ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	52.480m	47.564ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	52.480m	47.564ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	22.780s	2.394ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.957h	117.626ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.99	98.69	97.09	100.00	100.00	99.38	99.68

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
- Test alert_handler_stress_all_with_rand_reset has 11 failures.
  - 0.alert_handler_stress_all_with_rand_reset.63169598525671165997218295739156487402794490992250190630709654109204064090358
    Line 1080, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 603075800 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 603075800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.107751887475162918410198241016433083061794296333675603563426369234636672109383
    Line 28060, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18205991273 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18205991273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 11.alert_handler_stress_all_with_rand_reset.96944644875313931104970464777802907090849341105944389766418782195927027458475
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e600f1e9-9af3-4209-9b46-699a2f3303fa
```
  - 49.alert_handler_stress_all_with_rand_reset.40965311392560872530267578777234152867730411302870665177013569995175632185634
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d40740ff-c992-44a8-8e57-c7e8b69bbfc2
```
- Test alert_handler_lpg has 3 failures.
  - 18.alert_handler_lpg.36784230274459132931575920759871355608204607275385606988039355184804662062825
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_lpg/latest/run.log
```
  Job ID: smart:db60b7ce-9188-4459-8f7b-429d883d8983
```
  - 21.alert_handler_lpg.37300401466128618319140839114867028345084041996383058816546067727613740340694
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_lpg/latest/run.log
```
  Job ID: smart:5d5e436a-b98b-44b3-908a-a74c625185ea
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 15.alert_handler_stress_all_with_rand_reset.115090860206980282994669928465330722769365827025316449655776078376709183349041
    Line 13006, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 156626334271 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 156626334271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.alert_handler_stress_all_with_rand_reset.109931554977830806951435002934359508381409307330796186034152130701949813244674
    Line 83072, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106619470557 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 106619470557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 4.alert_handler_stress_all_with_rand_reset.1940587349828455519127056333161958510652250335237382199271186478922073233320
    Line 180863, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89012856972 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (4 [0x4] vs 251 [0xfb])
  UVM_INFO @ 89012856972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 19.alert_handler_lpg.3825751908190703462409707808984882171470218319659472727110412929823977603119
    Line 34277, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_lpg/latest/run.log
```
  UVM_ERROR @ 21572849769 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (209 [0xd1] vs 208 [0xd0]) reg name: alert_handler_reg_block.classb_accum_cnt
  UVM_INFO @ 21572849769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:497) [alert_handler_esc_intr_timeout_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 30.alert_handler_stress_all_with_rand_reset.51711020057104664463735864872770978457983350666717417853447178236982246652066
    Line 41473, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12637166971 ps: (cip_base_vseq.sv:497) [uvm_test_top.env.virtual_sequencer.alert_handler_esc_intr_timeout_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 12637166971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 46.alert_handler_stress_all_with_rand_reset.45627163375231724112547170115140427443788575351327783323399189375460842835150
    Line 124946, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132163146715 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 132163146715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9b7e615a7`