625f353e9c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 10.520s | 139.447us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 9.820s | 135.665us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 7.193m | 11.909ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 3.652m | 3.332ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 14.040s | 255.922us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 9.820s | 135.665us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 3.652m | 3.332ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 4.795m | 28.288ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.369m | 2.613ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 51.620m | 53.706ms | 49 | 50 | 98.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.116m | 2.082ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.236m | 1.207ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 59.180s | 960.874us | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 11.150m | 58.869ms | 49 | 50 | 98.00 |
| V2 | lpg | alert_handler_lpg | 49.184m | 108.273ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 51.104m | 199.205ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.213h | 1.488s | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 48.430s | 4.899ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.730s | 58.669us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.690s | 12.724us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 21.920s | 1.213ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 21.920s | 1.213ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 10.520s | 139.447us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.820s | 135.665us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 3.652m | 3.332ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 46.780s | 1.908ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 10.520s | 139.447us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.820s | 135.665us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 3.652m | 3.332ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 46.780s | 1.908ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.404m | 5.903ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.404m | 5.903ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.404m | 5.903ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.404m | 5.903ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 17.342m | 59.963ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 43.590s | 312.850us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 43.590s | 312.850us | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.404m | 5.903ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.087m | 1.708ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.116m | 2.082ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 49.184m | 108.273ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.116m | 2.082ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 51.620m | 53.706ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 51.620m | 53.706ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 1.106m | 1.614ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 1.811h | 707.462ms | 30 | 50 | 60.00 |
| V3 | TOTAL | 30 | 50 | 60.00 | |||
| TOTAL | 826 | 850 | 97.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 11 | 73.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.26 | 99.99 | 98.69 | 97.09 | 100.00 | 100.00 | 99.38 | 99.64 |
UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
3.alert_handler_stress_all_with_rand_reset.66532405288127338561381220925785490650014907843805389410373513517741410803246
Line 14970, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 70623319450 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 70623319450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.alert_handler_stress_all_with_rand_reset.76858071593983357542637490765114502351795728034479233312829792715366325229772
Line 7927, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7704921491 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7704921491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
9.alert_handler_stress_all_with_rand_reset.60485501913830977350986599155675112697236494752104038804691596652462658007911
Line 32663, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 113789521312 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 113789521312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.alert_handler_stress_all_with_rand_reset.72916344260784490175949300026491467311685309102175504097546779259132632618788
Line 61518, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111923801853 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 111923801853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test alert_handler_lpg_stub_clk has 1 failures.
19.alert_handler_lpg_stub_clk.23193829734841306525045008901958641305995330441593821458299231189841677299302
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:2ada506f-301b-43ff-9cc6-6df7becefa93
Test alert_handler_entropy has 1 failures.
38.alert_handler_entropy.112372968420575745408607281889996522861130129312874833487568913784920974871751
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_entropy/latest/run.log
Job ID: smart:718e1945-913c-4963-b173-6d3ab6cb360d
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
2.alert_handler_sig_int_fail.1263536143796248826465155468580438453933523290904662537759721881932650802504
Line 335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 62518640 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 62518640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
37.alert_handler_ping_timeout.70953898336329813764959943346902066676688627282678077056056954388234855019308
Line 507, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 972879740 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (282 [0x11a] vs 235 [0xeb])
UVM_INFO @ 972879740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---