ALERT_HANDLER Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.320s	136.905us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.050s	251.044us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.194m	9.106ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.198m	9.375ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.070s	207.311us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.050s	251.044us	20	20	100.00
		alert_handler_csr_aliasing	4.198m	9.375ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.281m	22.460ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.067m	954.359us	50	50	100.00
V2	entropy	alert_handler_entropy	54.726m	50.598ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.180m	4.256ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.377m	4.929ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.421m	4.951ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.120m	27.571ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.811m	51.260ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.324m	707.448ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.049h	62.183ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.250s	3.633ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.100s	88.217us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.420s	34.795us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.040s	297.814us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.040s	297.814us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.320s	136.905us	5	5	100.00
		alert_handler_csr_rw	9.050s	251.044us	20	20	100.00
		alert_handler_csr_aliasing	4.198m	9.375ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.420s	510.803us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.320s	136.905us	5	5	100.00
		alert_handler_csr_rw	9.050s	251.044us	20	20	100.00
		alert_handler_csr_aliasing	4.198m	9.375ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.420s	510.803us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.476m	6.699ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.476m	6.699ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.476m	6.699ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.476m	6.699ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.526m	85.883ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
		alert_handler_tl_intg_err	1.429m	4.929ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.429m	4.929ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.476m	6.699ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	57.510s	2.209ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.180m	4.256ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.811m	51.260ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.180m	4.256ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.726m	50.598ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.726m	50.598ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	50.880s	1.224ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.886h	110.937ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.73	97.09	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 0.alert_handler_stress_all_with_rand_reset.31207014294085645549813596054019070042266549313620995302259307112895991975696
    Line 9604, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8558814648 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8558814648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.alert_handler_stress_all_with_rand_reset.65576864497790039350105593291859444540676513330094835315358707856162622897643
    Line 13268, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121010409471 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 121010409471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
- Test alert_handler_stress_all has 1 failures.
  - 4.alert_handler_stress_all.4914656140691361073693986337191521689699622970403685014705806885409872604575
    Line 4358, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 2094620365 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 2094620365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_sig_int_fail has 1 failures.
  - 23.alert_handler_sig_int_fail.115040792070150953345648491988624636728318687964725942720235099421394655780823
    Line 500, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 118715868 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 118715868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 33.alert_handler_stress_all_with_rand_reset.56715376434315201900019002226021959846483602799293620680308320875788578154742
    Line 78918, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 249707694858 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 249707694858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.alert_handler_stress_all_with_rand_reset.20385019221594037333137650573633953463703054126297071355211128936117300474972
    Line 32219, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31957015696 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 31957015696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`