ALERT_HANDLER Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.540s	927.172us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.350s	255.928us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.779m	11.887ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.379m	1.219ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.020s	167.929us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.350s	255.928us	20	20	100.00
		alert_handler_csr_aliasing	2.379m	1.219ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.366m	8.205ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.153m	1.135ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.565m	243.263ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.061m	3.978ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.116m	1.269ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.277m	5.859ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.021m	65.343ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.021m	52.322ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.167m	221.703ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.051h	63.907ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	40.700s	3.789ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.860s	47.709us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.700s	11.184us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.810s	360.995us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.810s	360.995us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.540s	927.172us	5	5	100.00
		alert_handler_csr_rw	11.350s	255.928us	20	20	100.00
		alert_handler_csr_aliasing	2.379m	1.219ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.110s	1.217ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.540s	927.172us	5	5	100.00
		alert_handler_csr_rw	11.350s	255.928us	20	20	100.00
		alert_handler_csr_aliasing	2.379m	1.219ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.110s	1.217ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.463m	8.291ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.463m	8.291ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.463m	8.291ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.463m	8.291ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.399m	35.251ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
		alert_handler_tl_intg_err	47.970s	357.599us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	47.970s	357.599us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.463m	8.291ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.241m	2.435ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.061m	3.978ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.021m	52.322ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.061m	3.978ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.565m	243.263ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.565m	243.263ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.810s	1.122ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.995h	384.860ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			825	850	97.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	99.97	98.73	97.09	100.00	99.99	99.38	99.36

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test alert_handler_stress_all_with_rand_reset has 22 failures.
  - 1.alert_handler_stress_all_with_rand_reset.52527473538933457167450338946235501025251735213711363783715441136705860036741
    Line 14733, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91367921503 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91367921503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.alert_handler_stress_all_with_rand_reset.106998031057513818782175331417712236826954077691290067963661640311010427113798
    Line 81487, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 269268816304 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 269268816304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 20.alert_handler_stress_all.55093671917678675931650919905282024293244259899209951609384734689946348153675
    Line 2143, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 1343950312 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1343950312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 36.alert_handler_stress_all.10125696404078799886813420233711901195709010781218332560031206619449369056267
    Line 337, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @  39876813 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  39876813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 47.alert_handler_sig_int_fail.67209499319848291495779751073972751627756422136229242865974502627633907735056
    Line 605, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 189936901 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (410 [0x19a] vs 843 [0x34b])
  UVM_INFO @ 189936901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`