ALERT_HANDLER Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.760s	296.689us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.610s	528.042us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.409m	81.496ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.602m	47.239ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.890s	477.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.610s	528.042us	20	20	100.00
		alert_handler_csr_aliasing	5.602m	47.239ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.693m	4.808ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.187m	4.290ms	50	50	100.00
V2	entropy	alert_handler_entropy	45.348m	182.775ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	56.820s	1.040ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.056m	876.149us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.171m	6.381ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.714m	31.125ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.986m	122.286ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.166m	913.632ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.009h	62.028ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.920s	1.253ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.790s	49.469us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.450s	38.246us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.500s	704.579us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.500s	704.579us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.760s	296.689us	5	5	100.00
		alert_handler_csr_rw	9.610s	528.042us	20	20	100.00
		alert_handler_csr_aliasing	5.602m	47.239ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.400s	2.976ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.760s	296.689us	5	5	100.00
		alert_handler_csr_rw	9.610s	528.042us	20	20	100.00
		alert_handler_csr_aliasing	5.602m	47.239ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.400s	2.976ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.672m	9.090ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.672m	9.090ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.672m	9.090ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.672m	9.090ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.672m	137.432ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
		alert_handler_tl_intg_err	1.432m	7.332ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.432m	7.332ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.672m	9.090ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.232m	1.738ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	56.820s	1.040ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.986m	122.286ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	56.820s	1.040ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	45.348m	182.775ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	45.348m	182.775ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.800s	436.647us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.376h	1.195s	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.71	97.09	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 3.alert_handler_stress_all_with_rand_reset.36621203259600008997405893752002071769516880334643330036989413556565506362510
      Line 8089, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48165230704 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 48165230704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.alert_handler_stress_all_with_rand_reset.112526373433624434146644211729170230770347191367526226908453602130160996071240
      Line 1799, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2644296486 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2644296486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 16.alert_handler_stress_all_with_rand_reset.59587145561206429913786922460644557293319903858154415804352705188092859036753
      Line 67923, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 180379845910 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 180379845910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 35.alert_handler_stress_all_with_rand_reset.56488657804760008491380022175051149549880844272276102917546684154190950355786
      Line 40282, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 145234172485 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 145234172485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 47.alert_handler_stress_all_with_rand_reset.62635707224476345116282345458781455107247772819460133978796719164981364232705
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:6bd0d3bf-6cf6-4b33-8bce-821e198af79e
      

Past Results

• Latest
• lint
• 2024.08.04_07.04.51
• 2024.08.03_09.16.40
• 2024.08.02_08.28.15
• 2024.08.01_09.56.05
• 2024.07.31_09.22.55
• 2024.07.30_09.41.49