ALERT_HANDLER Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.080s	191.983us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.090s	497.272us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.553m	16.472ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.639m	18.115ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.160s	1.495ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.090s	497.272us	20	20	100.00
		alert_handler_csr_aliasing	2.639m	18.115ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.411m	24.448ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.017m	2.960ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.079m	238.976ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.109m	4.121ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.070m	2.279ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.081m	4.365ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.638m	160.704ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.021m	312.146ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.037m	117.968ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.196h	73.610ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	46.180s	4.499ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.260s	305.758us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.780s	42.735us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.660s	339.189us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.660s	339.189us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.080s	191.983us	5	5	100.00
		alert_handler_csr_rw	9.090s	497.272us	20	20	100.00
		alert_handler_csr_aliasing	2.639m	18.115ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.580s	1.358ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.080s	191.983us	5	5	100.00
		alert_handler_csr_rw	9.090s	497.272us	20	20	100.00
		alert_handler_csr_aliasing	2.639m	18.115ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.580s	1.358ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.394m	60.568ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.394m	60.568ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.394m	60.568ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.394m	60.568ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.600m	47.286ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
		alert_handler_tl_intg_err	1.474m	1.303ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.474m	1.303ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.394m	60.568ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.038m	1.979ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.109m	4.121ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.021m	312.146ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.109m	4.121ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.079m	238.976ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.079m	238.976ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.970s	2.893ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.884h	425.090ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.72	97.09	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test alert_handler_stress_all_with_rand_reset has 10 failures.

    • 7.alert_handler_stress_all_with_rand_reset.6409677220930722264403206409131422971936762939271802214313995853494181704359
      Line 14572, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46873125568 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46873125568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.alert_handler_stress_all_with_rand_reset.63983599342068200885949552838018486611434665889270501005592572407149080941980
      Line 26669, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23332380827 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23332380827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 6.alert_handler_stress_all.56781206070114207913481274775214310505760662773731879826180242876241472458040
      Line 76734, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 144903243038 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 7 [0x7]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 144903243038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 15.alert_handler_stress_all_with_rand_reset.63660150852475811898188107544433017142775264717671915560641967842969760888313
      Line 666, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1505017216 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 1505017216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 17.alert_handler_stress_all_with_rand_reset.66087500068358339356564275181317206433668998120502478818543408344456634226671
      Line 100005, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 127097343988 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (30 [0x1e] vs 7 [0x7])
        UVM_INFO @ 127097343988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 19.alert_handler_stress_all_with_rand_reset.33970626199081410946478147920370408284697557626746122376583222194233402656555
      Line 15396, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16180659483 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 16180659483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 40.alert_handler_stress_all_with_rand_reset.18539889900351099769309429975419903036373917404257021840225929277689277475180
      Line 135810, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36664113319 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 36664113319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 49.alert_handler_stress_all_with_rand_reset.33529002716822961383368449369925247481374617234166229702466282885701856439071
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:981283d5-7952-4056-b4d4-00ba15fead54
      

Past Results

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