5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 12.660s | 1.878ms | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 10.190s | 135.795us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 4.539m | 6.534ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.220m | 45.880ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 15.350s | 197.163us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 10.190s | 135.795us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.220m | 45.880ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.703m | 12.008ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.160m | 3.940ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 51.232m | 94.936ms | 48 | 50 | 96.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.024m | 4.078ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.050m | 1.061ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.173m | 2.293ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 11.083m | 64.086ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 52.629m | 53.136ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 52.534m | 110.354ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.314h | 257.325ms | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 44.030s | 4.294ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.550s | 202.802us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.860s | 18.977us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.950s | 336.334us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.950s | 336.334us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 12.660s | 1.878ms | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.190s | 135.795us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.220m | 45.880ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 41.350s | 2.412ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 12.660s | 1.878ms | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.190s | 135.795us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.220m | 45.880ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 41.350s | 2.412ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.349m | 5.449ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.349m | 5.449ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.349m | 5.449ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.349m | 5.449ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 20.633m | 17.171ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.631m | 6.163ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.631m | 6.163ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.349m | 5.449ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.238m | 11.541ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.024m | 4.078ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 52.629m | 53.136ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.024m | 4.078ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 51.232m | 94.936ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 51.232m | 94.936ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 20.250s | 1.856ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.199h | 89.656ms | 26 | 50 | 52.00 |
| V3 | TOTAL | 26 | 50 | 52.00 | |||
| TOTAL | 822 | 850 | 96.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.24 | 99.99 | 98.67 | 97.09 | 100.00 | 100.00 | 99.38 | 99.56 |
UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
4.alert_handler_stress_all_with_rand_reset.109335127021756323314275678243822274474490440298729454588283087350437241244453
Line 47013, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 133862114692 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 133862114692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.alert_handler_stress_all_with_rand_reset.62551016774580939544495045741835249778549516565066676158612759102754569912258
Line 95015, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 162564206036 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 162564206036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
Test alert_handler_entropy has 2 failures.
17.alert_handler_entropy.32532177085014487477554240293336480456987378785195929160167416402138485907918
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_entropy/latest/run.log
Job ID: smart:3b2e3396-20e0-496f-8b01-09e23af93d44
44.alert_handler_entropy.92937322620529053850501930542255692094546599035523874454906614769070966423577
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_entropy/latest/run.log
Job ID: smart:0be65a1c-8c49-4a88-a093-fd958e15525c
Test alert_handler_lpg has 1 failures.
21.alert_handler_lpg.86491394889207225600497811204375849082814818011810015902425397343739642301192
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_lpg/latest/run.log
Job ID: smart:b1628a70-281b-49c4-9b03-2f2f253b5073
Test alert_handler_stress_all_with_rand_reset has 1 failures.
27.alert_handler_stress_all_with_rand_reset.15396402777795984578621663734989208488113863456261490906337571136271592071872
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0de60681-bce5-48c3-b4ed-d067d4f26d89
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
6.alert_handler_stress_all_with_rand_reset.82230162782557321982823760728771389474584718303807772662651759976260434539732
Line 24443, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11594949186 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 11594949186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.alert_handler_stress_all_with_rand_reset.81528644282590806227476008407695253847437708604205254044380843406124620558272
Line 78160, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21172408668 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 21172408668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
28.alert_handler_sig_int_fail.66467273677880042334725740747233455746168141496670642342175243153967370847657
Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 122008702 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 122008702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---