ALERT_HANDLER Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.820s	127.825us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.280s	1.221ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.427m	15.481ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.819m	4.298ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.970s	620.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.280s	1.221ms	20	20	100.00
		alert_handler_csr_aliasing	4.819m	4.298ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.841m	71.832ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.363m	2.893ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.189m	131.276ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.046m	3.366ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.314m	1.241ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.202m	1.249ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.241m	73.879ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.198m	52.639ms	49	50	98.00
		alert_handler_lpg_stub_clk	57.701m	75.675ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.396h	313.325ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.037m	2.878ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.490s	242.949us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.530s	69.289us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.340s	615.927us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.340s	615.927us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.820s	127.825us	5	5	100.00
		alert_handler_csr_rw	10.280s	1.221ms	20	20	100.00
		alert_handler_csr_aliasing	4.819m	4.298ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.640s	1.510ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.820s	127.825us	5	5	100.00
		alert_handler_csr_rw	10.280s	1.221ms	20	20	100.00
		alert_handler_csr_aliasing	4.819m	4.298ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.640s	1.510ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.858m	6.529ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.858m	6.529ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.858m	6.529ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.858m	6.529ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.460m	112.453ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
		alert_handler_tl_intg_err	1.382m	6.533ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.382m	6.533ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.858m	6.529ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.192m	2.222ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.046m	3.366ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.198m	52.639ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.046m	3.366ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.189m	131.276ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.189m	131.276ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.370s	2.003ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.571h	197.310ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	99.99	98.64	97.06	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
- Test alert_handler_stress_all_with_rand_reset has 12 failures.
  - 0.alert_handler_stress_all_with_rand_reset.56882367438613422739640279020406983891984139476139785837942136698409497340387
    Line 420, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109345778 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 109345778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.44702506635124960965082535435104794967929612039842424249274644563257204522237
    Line 1089, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2759947356 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2759947356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 23.alert_handler_stress_all_with_rand_reset.79163113681712140209177037311037475894551626767650882734327141552811920818746
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1f948a2b-903a-49ef-8826-d4a9fd1a3291
```
- Test alert_handler_lpg has 1 failures.
  - 39.alert_handler_lpg.78430203009414306626484734386571578181176113694233382061479052484627444114088
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg/latest/run.log
```
  Job ID: smart:88d36667-8f6f-42f8-9d2f-4909e9e0ddc0
```
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 42.alert_handler_lpg_stub_clk.38861590564927047758982149996286678154573738246775162859479326818653172379334
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:fca2de72-0610-4ddf-afd1-dfb398c451bc
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 1.alert_handler_stress_all_with_rand_reset.109485780709491010396717742842522341404747504716503822954821087921968824083921
    Line 34029, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8635702110 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 8635702110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 35.alert_handler_sig_int_fail.16554564608442824200359671388037265886505748403545726221540852664556458876014
    Line 457, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  41282764 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (119 [0x77] vs 307 [0x133])
  UVM_INFO @  41282764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 43.alert_handler_stress_all_with_rand_reset.6555238137276840588410915507586334824201478333421007904543666144686803342077
    Line 25899, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25447653811 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 25447653811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `bbf435ceff`