ALERT_HANDLER Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.380s	790.288us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.930s	490.856us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.468m	5.700ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.947m	12.867ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.560s	625.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.930s	490.856us	20	20	100.00
		alert_handler_csr_aliasing	3.947m	12.867ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.813m	4.113ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.164m	6.299ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.617m	205.256ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	58.830s	807.400us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.271m	1.308ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.320m	2.333ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.041m	63.080ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.009m	252.357ms	49	50	98.00
		alert_handler_lpg_stub_clk	51.927m	234.621ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	59.023m	115.244ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	48.710s	4.725ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.250s	100.868us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.160s	22.357us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.000s	1.624ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.000s	1.624ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.380s	790.288us	5	5	100.00
		alert_handler_csr_rw	9.930s	490.856us	20	20	100.00
		alert_handler_csr_aliasing	3.947m	12.867ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.950s	2.588ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.380s	790.288us	5	5	100.00
		alert_handler_csr_rw	9.930s	490.856us	20	20	100.00
		alert_handler_csr_aliasing	3.947m	12.867ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.950s	2.588ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.987m	51.843ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.987m	51.843ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.987m	51.843ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.987m	51.843ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.933m	75.854ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
		alert_handler_tl_intg_err	1.118m	982.039us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.118m	982.039us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.987m	51.843ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.306m	1.308ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	58.830s	807.400us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.009m	252.357ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	58.830s	807.400us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.617m	205.256ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.617m	205.256ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	22.190s	712.645us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.632h	177.980ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.69	97.09	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test alert_handler_stress_all_with_rand_reset has 16 failures.

    • 0.alert_handler_stress_all_with_rand_reset.44306828617695479472012378946957855432852327399395622570828162431366888036055
      Line 419, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107211157 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 107211157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.27871938545986724241755510123887036168115020182188565290926809322191622559162
      Line 37253, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71034951969 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 71034951969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:475) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 2.alert_handler_lpg.26825272238878530506511972269227341361436722384192191728286901981887341352258
      Line 902, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_lpg/latest/run.log

        UVM_ERROR @ 1802404037 ps: (alert_handler_scoreboard.sv:475) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (7 [0x7] vs 15 [0xf]) reg name: intr_state
        UVM_INFO @ 1802404037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 26.alert_handler_stress_all_with_rand_reset.27079088365795558586863004888326680371506230707150975403393123992235558192116
      Line 29317, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 208716903630 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 208716903630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.08_09.23.28
• 2024.08.07_09.17.41
• 2024.08.06_09.44.54
• 2024.08.05_11.17.02
• 2024.08.04_07.04.51
• 2024.08.03_09.16.40