ALERT_HANDLER Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.840s	199.062us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.910s	217.686us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.146m	32.903ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.227m	20.865ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.290s	357.814us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.910s	217.686us	20	20	100.00
		alert_handler_csr_aliasing	4.227m	20.865ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.157m	22.484ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.186m	1.225ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.409m	54.923ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	59.520s	904.609us	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.229m	1.136ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.331m	4.824ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.343m	84.577ms	49	50	98.00
V2	lpg	alert_handler_lpg	53.819m	255.413ms	50	50	100.00
		alert_handler_lpg_stub_clk	45.997m	45.901ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.113h	295.535ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.215m	8.619ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.100s	49.050us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.830s	77.416us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.680s	701.165us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.680s	701.165us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.840s	199.062us	5	5	100.00
		alert_handler_csr_rw	8.910s	217.686us	20	20	100.00
		alert_handler_csr_aliasing	4.227m	20.865ms	5	5	100.00
		alert_handler_same_csr_outstanding	37.910s	2.824ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.840s	199.062us	5	5	100.00
		alert_handler_csr_rw	8.910s	217.686us	20	20	100.00
		alert_handler_csr_aliasing	4.227m	20.865ms	5	5	100.00
		alert_handler_same_csr_outstanding	37.910s	2.824ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.523m	8.098ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.523m	8.098ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.523m	8.098ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.523m	8.098ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.625m	67.864ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
		alert_handler_tl_intg_err	1.418m	2.572ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.418m	2.572ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.523m	8.098ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.262m	16.469ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	59.520s	904.609us	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.819m	255.413ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	59.520s	904.609us	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.409m	54.923ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.409m	54.923ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.075m	1.446ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.837h	435.580ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			837	850	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	99.99	98.61	97.09	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test alert_handler_stress_all_with_rand_reset has 7 failures.
  - 9.alert_handler_stress_all_with_rand_reset.23703167785232109328885639784727472374660895021201052640933566393846381157781
    Line 34366, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24296776196 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24296776196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.alert_handler_stress_all_with_rand_reset.114532382482817220655142321734578376174743821899141381754952518497017849903146
    Line 26483, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21138931139 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21138931139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
- Test alert_handler_ping_timeout has 1 failures.
  - 10.alert_handler_ping_timeout.30900613409205488569016818201813323980119333244955781413241662345555431028152
    Line 758, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log
```
  UVM_ERROR @ 4998570003 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 4998570003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 17.alert_handler_stress_all_with_rand_reset.64283850755177041511103510974117035159580248072745541352091281021989493906293
    Line 30783, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103851650753 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 103851650753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 12.alert_handler_stress_all_with_rand_reset.95955840103943366865598699714703372018380080195175090287566497233712143289447
    Line 8984, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14564651786 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classc_state
  UVM_INFO @ 14564651786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 17.alert_handler_sig_int_fail.22543762568914770963271128788723909393440599244736633542949052509496589905961
    Line 1074, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 530005433 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 7 [0x7]) reg name: alert_handler_reg_block.classa_state
  UVM_INFO @ 530005433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 23.alert_handler_stress_all_with_rand_reset.74100166972658425850541795950502400939789307490848216643987443331439484274600
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:36fcde53-e298-4c60-be37-5dc469fbdc30
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 45.alert_handler_sig_int_fail.99501490727814666551225580656254928050700039526786652048236449687477443237410
    Line 665, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 2704958313 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 2704958313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`