ALERT_HANDLER Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.450s	340.894us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.410s	551.405us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.100m	5.813ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.711m	4.707ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.660s	612.049us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.410s	551.405us	20	20	100.00
		alert_handler_csr_aliasing	5.711m	4.707ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.229m	5.743ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	57.400s	6.574ms	50	50	100.00
V2	entropy	alert_handler_entropy	48.861m	50.372ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.049m	2.026ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.308m	2.449ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.217m	5.123ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.144m	72.910ms	50	50	100.00
V2	lpg	alert_handler_lpg	46.118m	308.696ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.739m	55.869ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.282h	74.656ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	49.210s	1.171ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.720s	56.362us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.690s	12.198us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.860s	325.043us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.860s	325.043us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.450s	340.894us	5	5	100.00
		alert_handler_csr_rw	10.410s	551.405us	20	20	100.00
		alert_handler_csr_aliasing	5.711m	4.707ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.810s	2.374ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.450s	340.894us	5	5	100.00
		alert_handler_csr_rw	10.410s	551.405us	20	20	100.00
		alert_handler_csr_aliasing	5.711m	4.707ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.810s	2.374ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.266m	7.002ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.266m	7.002ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.266m	7.002ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.266m	7.002ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.008m	62.482ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
		alert_handler_tl_intg_err	1.523m	5.678ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.523m	5.678ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.266m	7.002ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.241m	2.473ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.049m	2.026ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	46.118m	308.696ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.049m	2.026ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	48.861m	50.372ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	48.861m	50.372ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.270s	441.043us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.945h	471.493ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.21	99.99	98.70	97.09	100.00	100.00	99.38	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 4.alert_handler_stress_all_with_rand_reset.25754957381542530986337234825044609642579615510568238040470954038162260306616
    Line 11883, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44061901423 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 44061901423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.alert_handler_stress_all_with_rand_reset.29872595181183058627117170221655046592873254065020315339968161139641636816545
    Line 16211, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153935874477 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 153935874477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 3 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 10.alert_handler_stress_all_with_rand_reset.100770709164888997944878725617526100065403744499893698946736808461338156666913
    Line 61212, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76126476007 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 76126476007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.alert_handler_stress_all_with_rand_reset.112662842755161069258698599013586872984850636820518804703185481253024421836078
    Line 158042, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 360767004121 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 360767004121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test alert_handler_sig_int_fail has 1 failures.
  - 23.alert_handler_sig_int_fail.18957857212719851594489882070629935677753739137446714915719179021138818183556
    Line 336, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  82073292 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  82073292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 5.alert_handler_stress_all_with_rand_reset.17847494150671135215418611052300305950476212550174361474323790926677653635216
    Line 26194, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42009039261 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 42009039261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.alert_handler_stress_all_with_rand_reset.113313220926685330493973079836957295622989717338862828504211934998464243279261
    Line 25963, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 158449369458 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 158449369458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 31.alert_handler_stress_all.59187519352481250034356157708403578675912937707847439406485638665638127790798
    Line 73426, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 11667173205 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 11667173205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`