ALERT_HANDLER Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.060s	494.751us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.450s	126.216us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.716m	2.071ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.690m	6.285ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.910s	817.005us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.450s	126.216us	20	20	100.00
		alert_handler_csr_aliasing	5.690m	6.285ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.083m	14.888ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.321m	7.976ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.991m	58.489ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.305m	16.514ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.245m	2.041ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.256m	4.574ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.042m	30.590ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.843m	63.974ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.239m	49.849ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.113h	69.935ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.228m	3.427ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	5.370s	218.462us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.820s	13.351us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.000s	1.068ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.000s	1.068ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.060s	494.751us	5	5	100.00
		alert_handler_csr_rw	11.450s	126.216us	20	20	100.00
		alert_handler_csr_aliasing	5.690m	6.285ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.460s	692.096us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.060s	494.751us	5	5	100.00
		alert_handler_csr_rw	11.450s	126.216us	20	20	100.00
		alert_handler_csr_aliasing	5.690m	6.285ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.460s	692.096us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.173m	5.367ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.173m	5.367ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.173m	5.367ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.173m	5.367ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.214m	67.169ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
		alert_handler_tl_intg_err	1.317m	2.537ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.317m	2.537ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.173m	5.367ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.189m	1.122ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.305m	16.514ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.843m	63.974ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.305m	16.514ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.991m	58.489ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.991m	58.489ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	40.350s	957.736us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.963h	452.510ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			836	850	98.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.70	97.09	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
- Test alert_handler_stress_all_with_rand_reset has 11 failures.
  - 1.alert_handler_stress_all_with_rand_reset.36421450592065745227148486863182753913296740906204439662985525092560556290003
    Line 21911, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41920343168 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41920343168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.alert_handler_stress_all_with_rand_reset.64457588771074475829841108631029062992882764514732857236735970916714777638157
    Line 83577, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 68333410872 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 68333410872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 20.alert_handler_stress_all_with_rand_reset.11490015978301366302621941372507278946890580464219764194909794813106645956589
    Line 38283, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48712239587 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 48712239587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 31.alert_handler_sig_int_fail.108626021915028675052203077681223746936905572569033449656318753980188233139676
    Line 745, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 357024132 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (318 [0x13e] vs 332 [0x14c])
  UVM_INFO @ 357024132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 35.alert_handler_stress_all.98690411782084932757274008240918601656259825706448861851265269283470516248352
    Line 419, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 365104016 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 365104016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`