ALERT_HANDLER Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.790s	113.882us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.030s	193.569us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.606m	21.053ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.257m	3.813ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.010s	552.450us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.030s	193.569us	20	20	100.00
		alert_handler_csr_aliasing	4.257m	3.813ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.857m	20.555ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.097m	7.351ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.393m	233.047ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.072m	4.449ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.033m	2.319ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.079m	2.055ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.375m	59.310ms	50	50	100.00
V2	lpg	alert_handler_lpg	49.239m	54.570ms	50	50	100.00
		alert_handler_lpg_stub_clk	51.397m	51.806ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.074h	258.666ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	52.120s	1.260ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.210s	203.027us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.690s	14.094us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.940s	410.065us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.940s	410.065us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.790s	113.882us	5	5	100.00
		alert_handler_csr_rw	10.030s	193.569us	20	20	100.00
		alert_handler_csr_aliasing	4.257m	3.813ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.510s	2.935ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.790s	113.882us	5	5	100.00
		alert_handler_csr_rw	10.030s	193.569us	20	20	100.00
		alert_handler_csr_aliasing	4.257m	3.813ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.510s	2.935ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.580m	5.420ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.580m	5.420ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.580m	5.420ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.580m	5.420ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.116m	12.729ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
		alert_handler_tl_intg_err	1.476m	6.243ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.476m	6.243ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.580m	5.420ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.297m	12.350ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.072m	4.449ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	49.239m	54.570ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.072m	4.449ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.393m	233.047ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.393m	233.047ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.006m	2.676ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	8.883m	17.262ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			823	850	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.77	97.09	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:848) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test alert_handler_stress_all_with_rand_reset has 21 failures.
  - 0.alert_handler_stress_all_with_rand_reset.104214913692687395023413788791615643806790903795095666084324284486842350297410
    Line 4557, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2884604016 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2884604016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.79562959730254290204719876020399148381275462936682288967085271190103466028551
    Line 2498, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6039602291 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6039602291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:767) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 7.alert_handler_stress_all_with_rand_reset.104323434452500180316371194271475042064267277933667691303529062187379861304116
    Line 3976, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38581822052 ps: (cip_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 38581822052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.alert_handler_stress_all_with_rand_reset.59510920045299556527332558703433981345596345632018629044432280872430138843718
    Line 1578, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1166317607 ps: (cip_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1166317607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 25.alert_handler_lpg_stub_clk.101205543231616384892739159269728035751550221305546406386520638676386764407014
    Line 67324, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 29.alert_handler_stress_all_with_rand_reset.44663214499415192941899021017571358681654592850591117164612983026860849891787
    Line 8147, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29768424150 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (629 [0x275] vs 794 [0x31a])
  UVM_INFO @ 29768424150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 31.alert_handler_sig_int_fail.79648724041126663927886131160412735333008827204289276377443508712098615771398
    Line 582, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 877871770 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 5 [0x5]) reg name: alert_handler_reg_block.classc_state
  UVM_INFO @ 877871770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 40.alert_handler_stress_all_with_rand_reset.31346008114253260729165020278700693681968646528712503752392468116561723770689
    Line 505, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 443165206 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 443165206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c082b8981f`